// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
// 
// Redistribution and use in source and binary forms, with or without
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// met:
// 
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// 
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//       with the distribution.
// 
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//       nor the names of its contributors may be used to endorse or
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename:            altera.vh
// Version:             1.0
// Verilog Standard:    Verilog-2001
// Description:         The altera.vh file is a header file that defines
// various ALTERA-specific primitives.
// Author:              Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`ifndef __ALTERA_VH
`define __ALTERA_VH 1

`define TLCFG_DEVCTL_I `SIG_CFG_ADD_W'h0 
`define TLCFG_LNKCTL_I `SIG_CFG_ADD_W'h2
`define TLCFG_PRMCMD_I `SIG_CFG_ADD_W'h3
`define TLCFG_MSICSR_I `SIG_CFG_ADD_W'hD
`define TLCFG_BUSDEV_I `SIG_CFG_ADD_W'hF

`define TLSTS_LWIDTH_R 40:35
`define TLSTS_LRATE_R 34:31

`define TLCTL_MAXREQ_R 30:28
`define TLCTL_MAXPAY_R 23:21
`define TLCTL_RCB_R 19:19
`define TLCTL_BUSMSTR_R 10:10
`define TLCTL_MSIENABLE_R 0:0
`define TLCTL_BUSDEV_R 12:0

`define SIG_CFG_STS_W 53
`define SIG_CFG_CTL_W 32
`define SIG_CFG_ADD_W 4

`define SIG_KO_CPLD_W 12
`define SIG_KO_CPLH_W 8
`endif