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//----------------------------------------------------------------------------
// Filename:			counter.v
// Version:				1.00.a
// Verilog Standard:	Verilog-2001
// Description: A simple up-counter. The maximum value is the largest expected
// value. The counter will not pass the SAT_VALUE. If the SAT_VALUE > MAX_VALUE,
// the counter will roll over and never stop. On RST_IN, the counter
// synchronously resets to the RST_VALUE
// Author:				Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "functions.vh"
module counter
    #(parameter C_MAX_VALUE = 10,
      parameter C_SAT_VALUE = 10,
      parameter C_RST_VALUE = 0)
    (
     input                              CLK,
     input                              RST_IN,

     input                              ENABLE,
     output [clog2s(C_MAX_VALUE+1)-1:0] VALUE
     );
    wire                                wEnable;
    reg [clog2s(C_MAX_VALUE+1)-1:0]     wCtrValue;
    reg [clog2s(C_MAX_VALUE+1)-1:0]     rCtrValue;
    /* verilator lint_off WIDTH */
    assign wEnable = ENABLE & (C_SAT_VALUE > rCtrValue);
    /* verilator lint_on WIDTH */
    assign VALUE = rCtrValue;
    always @(posedge CLK) begin
        if(RST_IN) begin
            rCtrValue <= C_RST_VALUE[clog2s(C_MAX_VALUE+1)-1:0];
        end else if(wEnable) begin
            rCtrValue <= rCtrValue + 1;
        end
    end
endmodule