mirror of
https://github.com/KastnerRG/riffa.git
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184 lines
6.3 KiB
C
Executable File
184 lines
6.3 KiB
C
Executable File
#if !defined(_RIFFA_H_)
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#define _RIFFA_H_
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// Adjusts register offsets for each channel
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#define CHNL_REG(c, o) (((c)<<4) + o)
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// Register offsets
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#define RIFFA_RX_SG_LEN_REG 0x0
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#define RIFFA_RX_SG_ADDR_LO_REG 0x1
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#define RIFFA_RX_SG_ADDR_HI_REG 0x2
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#define RIFFA_RX_LEN_REG 0x3
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#define RIFFA_RX_OFFLAST_REG 0x4
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#define RIFFA_TX_SG_LEN_REG 0x5
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#define RIFFA_TX_SG_ADDR_LO_REG 0x6
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#define RIFFA_TX_SG_ADDR_HI_REG 0x7
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#define RIFFA_TX_LEN_REG 0x8
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#define RIFFA_TX_OFFLAST_REG 0x9
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#define RIFFA_INFO_REG 0xA
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#define RIFFA_IRQ_0_REG 0xB
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#define RIFFA_IRQ_1_REG 0xC
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#define RIFFA_RX_TNFR_LEN_REG 0xD
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#define RIFFA_TX_TNFR_LEN_REG 0xE
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// Size of common buffer for scatter gather elements
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#define RIFFA_MIN_SG_BUF_SIZE (4*1024)
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// Size of common buffer for receive data spill
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#define RIFFA_SPILL_BUF_SIZE (4*1024)
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// Maximum number of scatter gather elements for each transfer
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#define RIFFA_MIN_NUM_SG_ELEMS (200)
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// Maximum bus width (multiply by 32 to get bit width)
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#define RIFFA_MAX_BUS_WIDTH_PARAM (4)
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// Maximum DMA transfer size (in bytes).
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#define RIFFA_MAX_TNFR_LEN (0xFFFFFFFF)
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// Number of DMA channels supported
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#define RIFFA_MAX_NUM_CHNLS (12)
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// Maximum number of RIFFA FPGAs
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#define RIFFA_MAX_NUM_FPGAS (5)
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// The structure used to hold data transfer information
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typedef struct RIFFA_FPGA_CHNL_IO {
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UINT32 Id;
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UINT32 Chnl;
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UINT32 Length;
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UINT32 Offset;
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UINT32 Last;
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UINT64 Timeout;
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} RIFFA_FPGA_CHNL_IO, * PRIFFA_FPGA_CHNL_IO;
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// The structure used to hold FPGA information
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typedef struct RIFFA_FPGA_INFO {
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UINT32 num_fpgas;
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UINT32 id[RIFFA_MAX_NUM_FPGAS];
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UINT32 num_chnls[RIFFA_MAX_NUM_FPGAS];
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CHAR name[RIFFA_MAX_NUM_FPGAS][16];
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UINT32 vendor_id[RIFFA_MAX_NUM_FPGAS];
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UINT32 device_id[RIFFA_MAX_NUM_FPGAS];
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} RIFFA_FPGA_INFO, * PRIFFA_FPGA_INFO;
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// Struct for holding DMA transaction state
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typedef struct CHNL_DIR_STATE {
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LONG Ready;
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LONG InUse;
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LONG ReqdDone;
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UINT64 Length;
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UINT64 Offset;
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UINT32 Last;
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UINT64 Timeout;
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UINT64 Capacity;
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UINT64 Provided;
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UINT64 ProvidedPrev;
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UINT64 Confirmed;
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UINT64 ConfirmedPrev;
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UINT64 SpillAfter;
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PMDL Mdl;
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PSCATTER_GATHER_LIST SgList;
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UINT32 SgPos;
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WDFSPINLOCK SpinLock;
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WDFTIMER Timer;
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WDFQUEUE PendingQueue;
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WDFDMATRANSACTION DmaTransaction;
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WDFCOMMONBUFFER CommonBuffer;
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PULONG CommonBufferBase;
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PHYSICAL_ADDRESS CommonBufferBaseLA; // Logical Address
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} CHNL_DIR_STATE, *PCHNL_DIR_STATE;
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// Struct for holding interrupt signals and data
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typedef struct INTR_CHNL_DIR_DATA {
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BOOLEAN NewTxn;
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UINT32 OffLast;
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UINT32 Length;
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BOOLEAN SgRead;
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BOOLEAN Done;
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} INTR_CHNL_DIR_DATA, *PINTR_CHNL_DIR_DATA;
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// The device extension for the device object
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typedef struct _DEVICE_EXTENSION {
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WDFDEVICE Device;
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PULONG Bar0;
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UINT32 Bar0Length;
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UINT32 MaxNumScatterGatherElems;
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WDFINTERRUPT Interrupt;
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WDFDMAENABLER DmaEnabler;
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WDFQUEUE IoctlQueue;
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UINT32 NumChnls;
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UINT32 VendorId;
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UINT32 DeviceId;
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CHAR Name[16];
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INTR_CHNL_DIR_DATA IntrData[2 * RIFFA_MAX_NUM_CHNLS]; // Send is the first bank,
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CHNL_DIR_STATE Chnl[(2*RIFFA_MAX_NUM_CHNLS)]; // recv is the second bank
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WDFCOMMONBUFFER SpillBuffer;
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PUCHAR SpillBufferBase;
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PHYSICAL_ADDRESS SpillBufferBaseLA; // Logical Address
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} DEVICE_EXTENSION, *PDEVICE_EXTENSION;
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// The request extension for the request object
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typedef struct _REQUEST_EXTENSION {
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UINT32 Chnl;
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} REQUEST_EXTENSION, *PREQUEST_EXTENSION;
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// The timer extension for the timer object
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typedef struct _TIMER_EXTENSION {
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UINT32 Chnl;
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} TIMER_EXTENSION, *PTIMER_EXTENSION;
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// This will generate the function named RiffaGetDeviceContext to be used for
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// retreiving the DEVICE_EXTENSION pointer.
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WDF_DECLARE_CONTEXT_TYPE_WITH_NAME(DEVICE_EXTENSION, RiffaGetDeviceContext)
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// This will generate the function named RiffaGetTimerContext to be used for
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// retreiving the TIMER_EXTENSION pointer.
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WDF_DECLARE_CONTEXT_TYPE_WITH_NAME(TIMER_EXTENSION, RiffaGetTimerContext)
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// This will generate the function named RiffaGetRequestContext to be used for
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// retreiving the REQUEST_EXTENSION pointer.
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WDF_DECLARE_CONTEXT_TYPE_WITH_NAME(REQUEST_EXTENSION, RiffaGetRequestContext)
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// Function prototypes
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DRIVER_INITIALIZE DriverEntry;
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EVT_WDF_DRIVER_DEVICE_ADD RiffaEvtDeviceAdd;
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EVT_WDF_OBJECT_CONTEXT_CLEANUP RiffaEvtDriverContextCleanup;
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EVT_WDF_DEVICE_PREPARE_HARDWARE RiffaEvtDevicePrepareHardware;
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EVT_WDF_DEVICE_RELEASE_HARDWARE RiffaEvtDeviceReleaseHardware;
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NTSTATUS RiffaReadHardwareIds(IN PDEVICE_EXTENSION DevExt);
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EVT_WDF_INTERRUPT_ISR RiffaEvtInterruptIsr;
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EVT_WDF_INTERRUPT_DPC RiffaEvtInterruptDpc;
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BOOLEAN RiffaProcessInterrupt(IN PDEVICE_EXTENSION DevExt, IN UINT32 Offset, IN UINT32 Vect);
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EVT_WDF_IO_QUEUE_IO_DEVICE_CONTROL RiffaEvtIoDeviceControl;
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VOID RiffaIoctlSend(IN PDEVICE_EXTENSION DevExt, IN WDFREQUEST Request,
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IN size_t OutputBufferLength, IN size_t InputBufferLength);
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VOID RiffaIoctlRecv(IN PDEVICE_EXTENSION DevExt, IN WDFREQUEST Request,
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IN size_t OutputBufferLength, IN size_t InputBufferLength);
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VOID RiffaIoctlList(IN PDEVICE_EXTENSION DevExt, IN WDFREQUEST Request,
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IN size_t OutputBufferLength, IN size_t InputBufferLength);
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VOID RiffaIoctlReset(IN PDEVICE_EXTENSION DevExt, IN WDFREQUEST Request);
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VOID RiffaCompleteRequest(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl, IN NTSTATUS Status, IN BOOLEAN TimedOut);
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EVT_WDF_TIMER RiffaEvtTimerFunc;
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VOID RiffaStartRecvTransaction(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl);
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NTSTATUS RiffaStartDmaTransaction(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl,
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IN UINT64 Length, IN UINT64 Offset, IN WDF_DMA_DIRECTION DmaDirection);
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VOID RiffaProgramScatterGather(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl);
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VOID RiffaTransactionComplete(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl,
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IN UINT32 Transferred, IN NTSTATUS Status);
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VOID RiffaProgramSend(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl, IN UINT32 Length,
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IN UINT32 Offset, IN UINT32 Last);
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EVT_WDF_PROGRAM_DMA RiffaEvtProgramDma;
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#pragma warning(disable:4127) // avoid conditional expression is constant error with W4
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#endif
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