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24 lines
1.1 KiB
Tcl
24 lines
1.1 KiB
Tcl
# Oscillator Clocks
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create_clock -name CLK1_50 -period 20 [get_ports {CLK1_50}]
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create_clock -name CLK2_50 -period 20 [get_ports {CLK2_50}]
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create_clock -name CLK3_50 -period 20 [get_ports {CLK3_50}]
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# Refclk (100 MHz differential input)
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create_clock -period "100 MHz" -name {refclk} [get_ports {PCIE_REFCLK}]
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# 50 MHZ PLL Clock
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create_generated_clock -name clk50 -source [get_ports {CLK1_50}] [get_nets {*|altpll_component|auto_generated|wire_pll1_clk[0]}]
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# 125 MHZ PLL Clock
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create_generated_clock -name clk125 -multiply_by 5 -divide_by 2 -source [get_ports {CLK1_50}] [get_nets {*|altpll_component|auto_generated|wire_pll1_clk[1]}]
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# 250 MHZ PLL Clock
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create_generated_clock -name clk250 -multiply_by 5 -source [get_ports {CLK1_50}] [get_nets {*|altpll_component|auto_generated|wire_pll1_clk[2]}]
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derive_pll_clocks
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derive_clock_uncertainty
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# Imported from IP Compiler user guide
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set_clock_groups -exclusive -group [get_clocks { refclk*clkout }] -group [get_clocks { *div0*coreclkout}]
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set_clock_groups -exclusive -group [get_clocks { *central_clk_div0* }] -group [get_clocks { *_hssi_pcie_hip* }] -group [get_clocks { *central_clk_div1* }]
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