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135 lines
6.3 KiB
Tcl
135 lines
6.3 KiB
Tcl
# ----------------------------------------------------------------------
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# Copyright (c) 2016, The Regents of the University of California All
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# rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met:
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#
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# * Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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#
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# * Redistributions in binary form must reproduce the above
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# copyright notice, this list of conditions and the following
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# disclaimer in the documentation and/or other materials provided
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# with the distribution.
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#
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# * Neither the name of The Regents of the University of California
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# nor the names of its contributors may be used to endorse or
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# promote products derived from this software without specific
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# prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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# DAMAGE.
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# ----------------------------------------------------------------------
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#----------------------------------------------------------------------------
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# Filename: 7V3_Top.xdc
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# Version: 1.00.a
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# Verilog Standard: Verilog-2001
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# Description: Xilinx Design Constraints for the Alpha Data 7V3 board.
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# These constrain the PCIE_REFCLK, its DSBUF, LED Pins, and PCIE_RESET_N pin
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#
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# Author: Dustin Richmond (@darichmond)
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#-----------------------------------------------------------------------------
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#
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#########################################################################################################################
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# User Constraints
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#########################################################################################################################
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###############################################################################
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# User Time Names / User Time Groups / Time Specs
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###############################################################################
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###############################################################################
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# User Physical Constraints
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###############################################################################
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#
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# LED Status Indicators for Example Design.
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# LED 0-2 should be all ON if link is up and functioning correctly
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# LED 3 should be blinking if user application is receiving valid clock
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#
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#System Reset, User Reset, User Link Up, User Clk Heartbeat
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set_property PACKAGE_PIN AC33 [get_ports {LED[0]}]
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set_property PACKAGE_PIN V32 [get_ports {LED[1]}]
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set_property PACKAGE_PIN V33 [get_ports {LED[2]}]
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set_property PACKAGE_PIN AB31 [get_ports {LED[3]}]
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set_property PACKAGE_PIN AB32 [get_ports {LED[4]}]
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set_property PACKAGE_PIN U30 [get_ports {LED[5]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {LED[0]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {LED[1]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {LED[2]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {LED[3]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {LED[4]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {LED[5]}]
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set_false_path -to [get_ports -filter NAME=~LED*]
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#########################################################################################################################
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# End User Constraints
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#########################################################################################################################
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#
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#
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#
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#########################################################################################################################
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# PCIE Core Constraints
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#########################################################################################################################
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#
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# SYS reset (input) signal. The sys_reset_n signal should be
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# obtained from the PCI Express interface if possible. For
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# slot based form factors, a system reset signal is usually
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# present on the connector. For cable based form factors, a
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# system reset signal may not be available. In this case, the
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# system reset signal must be generated locally by some form of
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# supervisory circuit. You may change the IOSTANDARD and LOC
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# to suit your requirements and VCCO voltage banking rules.
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# Some 7 series devices do not have 3.3 V I/Os available.
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# Therefore the appropriate level shift is required to operate
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# with these devices that contain only 1.8 V banks.
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#
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set_property PACKAGE_PIN W27 [get_ports PCIE_RESET_N]
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set_property IOSTANDARD LVCMOS18 [get_ports PCIE_RESET_N]
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set_property PULLUP true [get_ports PCIE_RESET_N]
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#
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#
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# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n
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# signals are the PCI Express reference clock. Virtex-7 GT
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# Transceiver architecture requires the use of a dedicated clock
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# resources (FPGA input pins) associated with each GT Transceiver.
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# To use these pins an IBUFDS primitive (refclk_ibuf) is
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# instantiated in user's design.
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# Please refer to the Virtex-7 GT Transceiver User Guide
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# (UG) for guidelines regarding clock resource selection.
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#
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set_property LOC IBUFDS_GTE2_X1Y16 [get_cells refclk_ibuf]
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###############################################################################
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# Timing Constraints
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###############################################################################
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create_clock -period 10.000 -name pcie_refclk [get_pins refclk_ibuf/O]
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###############################################################################
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# Physical Constraints
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###############################################################################
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set_false_path -from [get_ports PCIE_RESET_N]
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###############################################################################
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# End
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###############################################################################
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