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riffa/fpga/riffa_hdl
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Dustin Richmond 4d0bc24319 Fixed a bug (uncovered by the clock ratio issue) where the tx_multiplexer would 
confuse the tx_port_monitor by returning too few or too many write-packet
acknowledgements, resulting in a hang (but correct data!).
2016-02-16 16:04:10 -08:00
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altera.vh
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async_fifo_fwft.v
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async_fifo.v
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channel_32.v
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channel_64.v
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channel_128.v
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channel.v
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chnl_tester.v
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counter.v
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cross_domain_signal.v
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demux.v
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engine_layer.v
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ff.v
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fifo_packer_32.v
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fifo_packer_64.v
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fifo_packer_128.v
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fifo.v
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functions.vh
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interrupt_controller.v
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interrupt.v
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mux.v
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offset_flag_to_one_hot.v
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offset_to_mask.v
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one_hot_mux.v
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pipeline.v
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ram_1clk_1w_1r.v
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ram_2clk_1w_1r.v
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recv_credit_flow_ctrl.v
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register.v
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registers.v
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reorder_queue_input.v
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reorder_queue_output.v
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reorder_queue.v
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reset_controller.v
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reset_extender.v
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riffa.mk
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riffa.v
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riffa.vh
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rotate.v
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rx_engine_classic.v
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rx_engine_ultrascale.v
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rx_port_32.v
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rx_port_64.v
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rx_port_128.v
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rx_port_channel_gate.v
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rx_port_reader.v
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rx_port_requester_mux.v
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rxc_engine_128.v
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rxc_engine_classic.v
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rxc_engine_ultrascale.v
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rxr_engine_128.v
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rxr_engine_classic.v
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rxr_engine_ultrascale.v
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schedules.vh
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scsdpram.v
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sg_list_reader_32.v
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sg_list_reader_64.v
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sg_list_reader_128.v
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sg_list_requester.v
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shiftreg.v
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sync_fifo.v
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syncff.v
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tlp.vh
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translation_altera.v
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translation_xilinx.v
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trellis.vh
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tx_alignment_pipeline.v
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tx_data_fifo.v
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tx_data_pipeline.v
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tx_engine.v
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tx_hdr_fifo.v
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tx_multiplexer_32.v
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tx_multiplexer_64.v
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tx_multiplexer_128.v
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tx_multiplexer.v
Fixed a bug (uncovered by the clock ratio issue) where the tx_multiplexer would
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tx_port_32.v
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tx_port_64.v
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tx_port_128.v
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tx_port_buffer_32.v
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tx_port_buffer_64.v
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tx_port_buffer_128.v
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tx_port_channel_gate_32.v
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tx_port_channel_gate_64.v
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tx_port_channel_gate_128.v
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tx_port_monitor_32.v
Fixed a bug where a clock ratio of less than 1:2 between the user-provided clock
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tx_port_monitor_64.v
Fixed a bug where a clock ratio of less than 1:2 between the user-provided clock
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tx_port_monitor_128.v
Fixed a bug where a clock ratio of less than 1:2 between the user-provided clock
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tx_port_writer.v
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txc_engine_classic.v
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txc_engine_ultrascale.v
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txr_engine_classic.v
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txr_engine_ultrascale.v
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types.vh
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ultrascale.vh
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widths.vh
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xilinx.vh
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