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127 lines
4.9 KiB
Verilog
127 lines
4.9 KiB
Verilog
// ----------------------------------------------------------------------
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// Copyright (c) 2016, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Filename: fifo_packer_64.v
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// Version: 1.00.a
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// Verilog Standard: Verilog-2001
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// Description: Packs 32 or 64 bit received data into a 64 bit wide FIFO.
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// Assumes the FIFO always has room to accommodate the data.
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// Author: Matt Jacobsen
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// History: @mattj: Version 2.0
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// Additional Comments:
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//-----------------------------------------------------------------------------
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`timescale 1ns/1ns
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module fifo_packer_64 (
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input CLK,
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input RST,
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input [63:0] DATA_IN, // Incoming data
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input [1:0] DATA_IN_EN, // Incoming data enable
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input DATA_IN_DONE, // Incoming data packet end
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input DATA_IN_ERR, // Incoming data error
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input DATA_IN_FLUSH, // End of incoming data
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output [63:0] PACKED_DATA, // Outgoing data
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output PACKED_WEN, // Outgoing data write enable
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output PACKED_DATA_DONE, // End of outgoing data packet
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output PACKED_DATA_ERR, // Error in outgoing data
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output PACKED_DATA_FLUSHED // End of outgoing data
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);
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reg [1:0] rPackedCount=0, _rPackedCount=0;
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reg rPackedDone=0, _rPackedDone=0;
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reg rPackedErr=0, _rPackedErr=0;
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reg rPackedFlush=0, _rPackedFlush=0;
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reg rPackedFlushed=0, _rPackedFlushed=0;
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reg [95:0] rPackedData=96'd0, _rPackedData=96'd0;
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reg [63:0] rDataIn=64'd0, _rDataIn=64'd0;
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reg [1:0] rDataInEn=0, _rDataInEn=0;
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reg [63:0] rDataMasked=64'd0, _rDataMasked=64'd0;
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reg [1:0] rDataMaskedEn=0, _rDataMaskedEn=0;
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assign PACKED_DATA = rPackedData[63:0];
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assign PACKED_WEN = rPackedCount[1];
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assign PACKED_DATA_DONE = rPackedDone;
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assign PACKED_DATA_ERR = rPackedErr;
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assign PACKED_DATA_FLUSHED = rPackedFlushed;
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// Buffers input data until 2 words are available, then writes 2 words out.
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wire [63:0] wMask = {64{1'b1}}<<(32*rDataInEn);
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wire [63:0] wDataMasked = ~wMask & rDataIn;
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always @ (posedge CLK) begin
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rPackedCount <= #1 (RST ? 2'd0 : _rPackedCount);
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rPackedDone <= #1 (RST ? 1'd0 : _rPackedDone);
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rPackedErr <= #1 (RST ? 1'd0 : _rPackedErr);
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rPackedFlush <= #1 (RST ? 1'd0 : _rPackedFlush);
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rPackedFlushed <= #1 (RST ? 1'd0 : _rPackedFlushed);
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rPackedData <= #1 (RST ? 96'd0 : _rPackedData);
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rDataIn <= #1 _rDataIn;
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rDataInEn <= #1 (RST ? 2'd0 : _rDataInEn);
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rDataMasked <= #1 _rDataMasked;
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rDataMaskedEn <= #1 (RST ? 2'd0 : _rDataMaskedEn);
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end
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always @ (*) begin
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// Buffer and mask the input data.
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_rDataIn = DATA_IN;
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_rDataInEn = DATA_IN_EN;
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_rDataMasked = wDataMasked;
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_rDataMaskedEn = rDataInEn;
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// Count what's in our buffer. When we reach 2 words, 2 words will be written
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// out. If flush is requested, write out whatever remains.
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if (rPackedFlush && rPackedCount[0])
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_rPackedCount = 2;
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else
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_rPackedCount = rPackedCount + rDataMaskedEn - {rPackedCount[1], 1'd0};
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// Shift data into and out of our buffer as we receive and write out data.
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if (rDataMaskedEn != 2'd0)
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_rPackedData = ((rPackedData>>(32*{rPackedCount[1], 1'd0})) | (rDataMasked<<(32*rPackedCount[0])));
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else
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_rPackedData = (rPackedData>>(32*{rPackedCount[1], 1'd0}));
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// Track done/error/flush signals.
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_rPackedDone = DATA_IN_DONE;
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_rPackedErr = DATA_IN_ERR;
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_rPackedFlush = DATA_IN_FLUSH;
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_rPackedFlushed = rPackedFlush;
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end
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endmodule
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