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196 lines
10 KiB
Verilog
196 lines
10 KiB
Verilog
// ----------------------------------------------------------------------
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// Copyright (c) 2016, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Filename: rx_engine_ultrascale.v
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// Version: 1.0
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// Verilog Standard: Verilog-2001
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// Description: The RX Engine (Ultrascale) takes a the two streams of
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// AXI from the Xilinx endpoint packets and provides the request packets on the
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// RXR Interface, and the completion packets on the RXC Interface.
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// This Engine is capable of operating at "line rate".
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// Author: Dustin Richmond (@darichmond)
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//-----------------------------------------------------------------------------
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`timescale 1ns/1ns
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`include "ultrascale.vh"
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`include "trellis.vh"
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module rx_engine_ultrascale
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#(parameter C_PCI_DATA_WIDTH = 128)
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(// Interface: Clocks
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input CLK, // Replacement for generic CLK
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// Interface: Resets
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input RST_BUS, // Replacement for generic RST_IN
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input RST_LOGIC, // Addition for RIFFA_RST
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output DONE_RXR_RST,
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output DONE_RXC_RST,
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// Interface: CQ
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input M_AXIS_CQ_TVALID,
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input M_AXIS_CQ_TLAST,
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input [C_PCI_DATA_WIDTH-1:0] M_AXIS_CQ_TDATA,
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input [(C_PCI_DATA_WIDTH/32)-1:0] M_AXIS_CQ_TKEEP,
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input [`SIG_CQ_TUSER_W-1:0] M_AXIS_CQ_TUSER,
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output M_AXIS_CQ_TREADY,
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// Interface: RC
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input M_AXIS_RC_TVALID,
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input M_AXIS_RC_TLAST,
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input [C_PCI_DATA_WIDTH-1:0] M_AXIS_RC_TDATA,
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input [(C_PCI_DATA_WIDTH/32)-1:0] M_AXIS_RC_TKEEP,
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input [`SIG_RC_TUSER_W-1:0] M_AXIS_RC_TUSER,
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output M_AXIS_RC_TREADY,
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// Interface: RXC Engine
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output [C_PCI_DATA_WIDTH-1:0] RXC_DATA,
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output RXC_DATA_VALID,
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output [(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_WORD_ENABLE,
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output RXC_DATA_START_FLAG,
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output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_START_OFFSET,
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output RXC_DATA_END_FLAG,
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output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_END_OFFSET,
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output [`SIG_LBE_W-1:0] RXC_META_LDWBE,
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output [`SIG_FBE_W-1:0] RXC_META_FDWBE,
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output [`SIG_TAG_W-1:0] RXC_META_TAG,
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output [`SIG_LOWADDR_W-1:0] RXC_META_ADDR,
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output [`SIG_TYPE_W-1:0] RXC_META_TYPE,
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output [`SIG_LEN_W-1:0] RXC_META_LENGTH,
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output [`SIG_BYTECNT_W-1:0] RXC_META_BYTES_REMAINING,
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output [`SIG_CPLID_W-1:0] RXC_META_COMPLETER_ID,
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output RXC_META_EP,
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// Interface: RXR Engine
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output [C_PCI_DATA_WIDTH-1:0] RXR_DATA,
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output RXR_DATA_VALID,
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output [(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_WORD_ENABLE,
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output RXR_DATA_START_FLAG,
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output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET,
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output RXR_DATA_END_FLAG,
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output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET,
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output [`SIG_FBE_W-1:0] RXR_META_FDWBE,
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output [`SIG_LBE_W-1:0] RXR_META_LDWBE,
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output [`SIG_TC_W-1:0] RXR_META_TC,
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output [`SIG_ATTR_W-1:0] RXR_META_ATTR,
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output [`SIG_TAG_W-1:0] RXR_META_TAG,
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output [`SIG_TYPE_W-1:0] RXR_META_TYPE,
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output [`SIG_ADDR_W-1:0] RXR_META_ADDR,
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output [`SIG_BARDECODE_W-1:0] RXR_META_BAR_DECODED,
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output [`SIG_REQID_W-1:0] RXR_META_REQUESTER_ID,
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output [`SIG_LEN_W-1:0] RXR_META_LENGTH,
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output RXR_META_EP
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);
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localparam C_RX_PIPELINE_DEPTH = 3;
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rxc_engine_ultrascale
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#(///*AUTOINSTPARAM*/
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// Parameters
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.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
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.C_RX_PIPELINE_DEPTH (C_RX_PIPELINE_DEPTH))
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rxc_engine_inst
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(/*AUTOINST*/
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// Outputs
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.DONE_RXC_RST (DONE_RXC_RST),
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.M_AXIS_RC_TREADY (M_AXIS_RC_TREADY),
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.RXC_DATA (RXC_DATA[C_PCI_DATA_WIDTH-1:0]),
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.RXC_DATA_VALID (RXC_DATA_VALID),
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.RXC_DATA_WORD_ENABLE (RXC_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
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.RXC_DATA_START_FLAG (RXC_DATA_START_FLAG),
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.RXC_DATA_START_OFFSET (RXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
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.RXC_DATA_END_FLAG (RXC_DATA_END_FLAG),
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.RXC_DATA_END_OFFSET (RXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
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.RXC_META_LDWBE (RXC_META_LDWBE[`SIG_LBE_W-1:0]),
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.RXC_META_FDWBE (RXC_META_FDWBE[`SIG_FBE_W-1:0]),
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.RXC_META_TAG (RXC_META_TAG[`SIG_TAG_W-1:0]),
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.RXC_META_ADDR (RXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
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.RXC_META_TYPE (RXC_META_TYPE[`SIG_TYPE_W-1:0]),
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.RXC_META_LENGTH (RXC_META_LENGTH[`SIG_LEN_W-1:0]),
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.RXC_META_BYTES_REMAINING (RXC_META_BYTES_REMAINING[`SIG_BYTECNT_W-1:0]),
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.RXC_META_COMPLETER_ID (RXC_META_COMPLETER_ID[`SIG_CPLID_W-1:0]),
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.RXC_META_EP (RXC_META_EP),
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// Inputs
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.CLK (CLK),
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.RST_BUS (RST_BUS),
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.RST_LOGIC (RST_LOGIC),
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.M_AXIS_RC_TVALID (M_AXIS_RC_TVALID),
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.M_AXIS_RC_TLAST (M_AXIS_RC_TLAST),
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.M_AXIS_RC_TDATA (M_AXIS_RC_TDATA[C_PCI_DATA_WIDTH-1:0]),
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.M_AXIS_RC_TKEEP (M_AXIS_RC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
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.M_AXIS_RC_TUSER (M_AXIS_RC_TUSER[`SIG_RC_TUSER_W-1:0]));
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rxr_engine_ultrascale
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#(/*AUTOINSTPARAM*/
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// Parameters
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.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
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.C_RX_PIPELINE_DEPTH (C_RX_PIPELINE_DEPTH))
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rxr_engine_inst
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(/*AUTOINST*/
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// Outputs
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.DONE_RXR_RST (DONE_RXR_RST),
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.M_AXIS_CQ_TREADY (M_AXIS_CQ_TREADY),
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.RXR_DATA (RXR_DATA[C_PCI_DATA_WIDTH-1:0]),
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.RXR_DATA_VALID (RXR_DATA_VALID),
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.RXR_DATA_WORD_ENABLE (RXR_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
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.RXR_DATA_START_FLAG (RXR_DATA_START_FLAG),
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.RXR_DATA_START_OFFSET (RXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
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.RXR_DATA_END_FLAG (RXR_DATA_END_FLAG),
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.RXR_DATA_END_OFFSET (RXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
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.RXR_META_FDWBE (RXR_META_FDWBE[`SIG_FBE_W-1:0]),
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.RXR_META_LDWBE (RXR_META_LDWBE[`SIG_LBE_W-1:0]),
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.RXR_META_TC (RXR_META_TC[`SIG_TC_W-1:0]),
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.RXR_META_ATTR (RXR_META_ATTR[`SIG_ATTR_W-1:0]),
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.RXR_META_TAG (RXR_META_TAG[`SIG_TAG_W-1:0]),
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.RXR_META_TYPE (RXR_META_TYPE[`SIG_TYPE_W-1:0]),
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.RXR_META_ADDR (RXR_META_ADDR[`SIG_ADDR_W-1:0]),
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.RXR_META_BAR_DECODED (RXR_META_BAR_DECODED[`SIG_BARDECODE_W-1:0]),
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.RXR_META_REQUESTER_ID (RXR_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
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.RXR_META_LENGTH (RXR_META_LENGTH[`SIG_LEN_W-1:0]),
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.RXR_META_EP (RXR_META_EP),
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// Inputs
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.CLK (CLK),
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.RST_BUS (RST_BUS),
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.RST_LOGIC (RST_LOGIC),
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.M_AXIS_CQ_TVALID (M_AXIS_CQ_TVALID),
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.M_AXIS_CQ_TLAST (M_AXIS_CQ_TLAST),
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.M_AXIS_CQ_TDATA (M_AXIS_CQ_TDATA[C_PCI_DATA_WIDTH-1:0]),
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.M_AXIS_CQ_TKEEP (M_AXIS_CQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
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.M_AXIS_CQ_TUSER (M_AXIS_CQ_TUSER[`SIG_CQ_TUSER_W-1:0]));
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endmodule // rx_engine_ultrascale
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// Local Variables:
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// verilog-library-directories:("." "./rx/")
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// End:
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