mirror of
https://github.com/KastnerRG/riffa.git
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4d0bc24319
confuse the tx_port_monitor by returning too few or too many write-packet acknowledgements, resulting in a hang (but correct data!).
307 lines
16 KiB
Verilog
307 lines
16 KiB
Verilog
// ----------------------------------------------------------------------
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// Copyright (c) 2016, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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// ----------------------------------------------------------------------
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// Filename: Filename: tx_multiplexer.v
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// Version: Version: 1.0
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// Verilog Standard: Verilog-2005
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// Description: the TX Multiplexer services read and write requests from
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// RIFFA channels in round robin order.
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// Author: Dustin Richmond (@darichmond)
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// ----------------------------------------------------------------------
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`include "trellis.vh"
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module tx_multiplexer
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#(
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parameter C_PCI_DATA_WIDTH = 128,
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parameter C_NUM_CHNL = 12,
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parameter C_TAG_WIDTH = 5,
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parameter C_VENDOR = "ALTERA",
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parameter C_DEPTH_PACKETS = 10
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)
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(
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input CLK,
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input RST_IN,
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input [C_NUM_CHNL-1:0] WR_REQ, // Write request
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input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] WR_ADDR, // Write address
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input [(C_NUM_CHNL*`SIG_LEN_W)-1:0] WR_LEN, // Write data length
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input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] WR_DATA, // Write data
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output [C_NUM_CHNL-1:0] WR_DATA_REN, // Write data read enable
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output [C_NUM_CHNL-1:0] WR_ACK, // Write request has been accepted
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output [C_NUM_CHNL-1:0] WR_SENT, // Write Reuqest has been sent to the core
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input [C_NUM_CHNL-1:0] RD_REQ, // Read request
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input [(C_NUM_CHNL*2)-1:0] RD_SG_CHNL, // Read request channel for scatter gather lists
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input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] RD_ADDR, // Read request address
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input [(C_NUM_CHNL*`SIG_LEN_W)-1:0] RD_LEN, // Read request length
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output [C_NUM_CHNL-1:0] RD_ACK, // Read request has been accepted
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output [5:0] INT_TAG, // Internal tag to exchange with external
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output INT_TAG_VALID, // High to signal tag exchange
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input [C_TAG_WIDTH-1:0] EXT_TAG, // External tag to provide in exchange for internal tag
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input EXT_TAG_VALID, // High to signal external tag is valid
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output TX_ENG_RD_REQ_SENT, // Read completion request issued
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input RXBUF_SPACE_AVAIL,
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// Interface: TXR Engine
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output TXR_DATA_VALID,
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output [C_PCI_DATA_WIDTH-1:0] TXR_DATA,
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output TXR_DATA_START_FLAG,
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output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
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output TXR_DATA_END_FLAG,
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output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
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input TXR_DATA_READY,
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output TXR_META_VALID,
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output [`SIG_FBE_W-1:0] TXR_META_FDWBE,
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output [`SIG_LBE_W-1:0] TXR_META_LDWBE,
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output [`SIG_ADDR_W-1:0] TXR_META_ADDR,
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output [`SIG_LEN_W-1:0] TXR_META_LENGTH,
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output [`SIG_TAG_W-1:0] TXR_META_TAG,
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output [`SIG_TC_W-1:0] TXR_META_TC,
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output [`SIG_ATTR_W-1:0] TXR_META_ATTR,
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output [`SIG_TYPE_W-1:0] TXR_META_TYPE,
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output TXR_META_EP,
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input TXR_META_READY,
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input TXR_SENT);
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wire [C_NUM_CHNL-1:0] wAckRdData;
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wire wAckValid;
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reg [C_NUM_CHNL-1:0] rAckWrData; // Registered fifo input (only write acks)
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reg [C_NUM_CHNL-1:0] rAckRdData; // Registered fifo output (only write acks)
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reg rAckWrEn,_rAckWrEn; // Fifo write enable (RD or WR_ACK)
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reg rAckRdEn; // Fifo read enable (TXR_SENT)
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always @(*) begin
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_rAckWrEn = (WR_ACK != 0);
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end
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always @(posedge CLK) begin
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rAckWrData <= WR_ACK;
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rAckWrEn <= _rAckWrEn;
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end
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always @(posedge CLK) begin
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rAckRdEn <= TXR_SENT;
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if(rAckRdEn) begin
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rAckRdData <= wAckRdData & {C_NUM_CHNL{wAckValid}};
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end else begin
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rAckRdData <= 0;
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end
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end
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assign WR_SENT = rAckRdData;
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fifo
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#(// Parameters
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.C_WIDTH (C_NUM_CHNL),
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.C_DEPTH (C_DEPTH_PACKETS*3), // This is an extremely conservative estimate...
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.C_DELAY (0)
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/*AUTOINSTPARAM*/)
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req_ack_fifo
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(// Outputs
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.WR_READY (),
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.RD_DATA (wAckRdData),
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.RD_VALID (wAckValid),
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// Inputs
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.WR_DATA (rAckWrData),
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.WR_VALID (rAckWrEn),
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.RD_READY (rAckRdEn),
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.RST (RST_IN),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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generate
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if(C_PCI_DATA_WIDTH == 32) begin
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tx_multiplexer_32
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#(/*AUTOINSTPARAM*/
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// Parameters
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.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
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.C_NUM_CHNL (C_NUM_CHNL),
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.C_TAG_WIDTH (C_TAG_WIDTH),
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.C_VENDOR (C_VENDOR))
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tx_mux
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(/*AUTOINST*/
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// Outputs
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.WR_DATA_REN (WR_DATA_REN[C_NUM_CHNL-1:0]),
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.WR_ACK (WR_ACK[C_NUM_CHNL-1:0]),
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.RD_ACK (RD_ACK[C_NUM_CHNL-1:0]),
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.INT_TAG (INT_TAG[5:0]),
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.INT_TAG_VALID (INT_TAG_VALID),
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.TX_ENG_RD_REQ_SENT (TX_ENG_RD_REQ_SENT),
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.TXR_DATA_VALID (TXR_DATA_VALID),
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.TXR_DATA (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
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.TXR_DATA_START_FLAG (TXR_DATA_START_FLAG),
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.TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
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.TXR_DATA_END_FLAG (TXR_DATA_END_FLAG),
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.TXR_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
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.TXR_META_VALID (TXR_META_VALID),
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.TXR_META_FDWBE (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
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.TXR_META_LDWBE (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
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.TXR_META_ADDR (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
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.TXR_META_LENGTH (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
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.TXR_META_TAG (TXR_META_TAG[`SIG_TAG_W-1:0]),
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.TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]),
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.TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
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.TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
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.TXR_META_EP (TXR_META_EP),
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN),
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.WR_REQ (WR_REQ[C_NUM_CHNL-1:0]),
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.WR_ADDR (WR_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
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.WR_LEN (WR_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
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.WR_DATA (WR_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
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.RD_REQ (RD_REQ[C_NUM_CHNL-1:0]),
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.RD_SG_CHNL (RD_SG_CHNL[(C_NUM_CHNL*2)-1:0]),
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.RD_ADDR (RD_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
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.RD_LEN (RD_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
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.EXT_TAG (EXT_TAG[C_TAG_WIDTH-1:0]),
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.EXT_TAG_VALID (EXT_TAG_VALID),
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.RXBUF_SPACE_AVAIL (RXBUF_SPACE_AVAIL),
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.TXR_DATA_READY (TXR_DATA_READY),
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.TXR_META_READY (TXR_META_READY));
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end else if(C_PCI_DATA_WIDTH == 64) begin
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tx_multiplexer_64
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#(/*AUTOINSTPARAM*/
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// Parameters
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.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
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.C_NUM_CHNL (C_NUM_CHNL),
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.C_TAG_WIDTH (C_TAG_WIDTH),
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.C_VENDOR (C_VENDOR))
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tx_mux
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(/*AUTOINST*/
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// Outputs
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.WR_DATA_REN (WR_DATA_REN[C_NUM_CHNL-1:0]),
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.WR_ACK (WR_ACK[C_NUM_CHNL-1:0]),
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.RD_ACK (RD_ACK[C_NUM_CHNL-1:0]),
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.INT_TAG (INT_TAG[5:0]),
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.INT_TAG_VALID (INT_TAG_VALID),
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.TX_ENG_RD_REQ_SENT (TX_ENG_RD_REQ_SENT),
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.TXR_DATA_VALID (TXR_DATA_VALID),
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.TXR_DATA (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
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.TXR_DATA_START_FLAG (TXR_DATA_START_FLAG),
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.TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
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.TXR_DATA_END_FLAG (TXR_DATA_END_FLAG),
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.TXR_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
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.TXR_META_VALID (TXR_META_VALID),
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.TXR_META_FDWBE (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
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.TXR_META_LDWBE (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
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.TXR_META_ADDR (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
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.TXR_META_LENGTH (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
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.TXR_META_TAG (TXR_META_TAG[`SIG_TAG_W-1:0]),
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.TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]),
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.TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
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.TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
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.TXR_META_EP (TXR_META_EP),
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN),
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.WR_REQ (WR_REQ[C_NUM_CHNL-1:0]),
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.WR_ADDR (WR_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
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.WR_LEN (WR_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
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.WR_DATA (WR_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
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.RD_REQ (RD_REQ[C_NUM_CHNL-1:0]),
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.RD_SG_CHNL (RD_SG_CHNL[(C_NUM_CHNL*2)-1:0]),
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.RD_ADDR (RD_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
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.RD_LEN (RD_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
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.EXT_TAG (EXT_TAG[C_TAG_WIDTH-1:0]),
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.EXT_TAG_VALID (EXT_TAG_VALID),
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.RXBUF_SPACE_AVAIL (RXBUF_SPACE_AVAIL),
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.TXR_DATA_READY (TXR_DATA_READY),
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.TXR_META_READY (TXR_META_READY));
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end else if(C_PCI_DATA_WIDTH == 128) begin
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tx_multiplexer_128
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#(/*AUTOINSTPARAM*/
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// Parameters
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.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
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.C_NUM_CHNL (C_NUM_CHNL),
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.C_TAG_WIDTH (C_TAG_WIDTH),
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.C_VENDOR (C_VENDOR))
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tx_mux_128_inst
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(/*AUTOINST*/
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// Outputs
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.WR_DATA_REN (WR_DATA_REN[C_NUM_CHNL-1:0]),
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.WR_ACK (WR_ACK[C_NUM_CHNL-1:0]),
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.RD_ACK (RD_ACK[C_NUM_CHNL-1:0]),
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.INT_TAG (INT_TAG[5:0]),
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.INT_TAG_VALID (INT_TAG_VALID),
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.TX_ENG_RD_REQ_SENT (TX_ENG_RD_REQ_SENT),
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.TXR_DATA_VALID (TXR_DATA_VALID),
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.TXR_DATA (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
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.TXR_DATA_START_FLAG (TXR_DATA_START_FLAG),
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.TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
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.TXR_DATA_END_FLAG (TXR_DATA_END_FLAG),
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.TXR_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
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.TXR_META_VALID (TXR_META_VALID),
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.TXR_META_FDWBE (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
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.TXR_META_LDWBE (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
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.TXR_META_ADDR (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
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.TXR_META_LENGTH (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
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.TXR_META_TAG (TXR_META_TAG[`SIG_TAG_W-1:0]),
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.TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]),
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.TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
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.TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
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.TXR_META_EP (TXR_META_EP),
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN),
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.WR_REQ (WR_REQ[C_NUM_CHNL-1:0]),
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.WR_ADDR (WR_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
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.WR_LEN (WR_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
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.WR_DATA (WR_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
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.RD_REQ (RD_REQ[C_NUM_CHNL-1:0]),
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.RD_SG_CHNL (RD_SG_CHNL[(C_NUM_CHNL*2)-1:0]),
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.RD_ADDR (RD_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
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.RD_LEN (RD_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
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.EXT_TAG (EXT_TAG[C_TAG_WIDTH-1:0]),
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.EXT_TAG_VALID (EXT_TAG_VALID),
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.RXBUF_SPACE_AVAIL (RXBUF_SPACE_AVAIL),
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.TXR_DATA_READY (TXR_DATA_READY),
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.TXR_META_READY (TXR_META_READY));
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end
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endgenerate
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endmodule
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// Local Variables:
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// verilog-library-directories:("." "registers/" "../common/")
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// End:
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