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FPGA
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riffa
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riffa
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fpga
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Dustin Richmond
2a832ffe4e
Fixed a bug in the TX Alignment Pipeline where two EOFs in a cycle from the Data
...
Fifo would cause corruption in subsequent transfers.
2016-02-02 17:14:29 -08:00
..
altera
Adding updated bit files and project files
2016-01-27 10:39:17 -08:00
riffa_hdl
Fixed a bug in the TX Alignment Pipeline where two EOFs in a cycle from the Data
2016-02-02 17:14:29 -08:00
xilinx
Adding updated bit files and project files
2016-01-27 10:39:17 -08:00
Makefile
Adding additional commands to base Makefile
2016-01-26 11:31:06 -08:00