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31b82c1777
The graceful reset logic splits the RST_IN port into the RST_BUS and RST_LOGIC ports. The RST_BUS port is for when the entire PCIe (or whatever) bus is undergoing reset and the RIFFA logic should not worry about corrupting any state by terminating a packet early (causing a malformed packet). RST_LOGIC is for logic resets, where PCIe state is not affected and may be corrupted by a malformed packet.
123 lines
4.4 KiB
Verilog
123 lines
4.4 KiB
Verilog
// ----------------------------------------------------------------------
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// Copyright (c) 2015, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Filename: trellis.vh
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// Version: 1.0
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// Verilog Standard: Verilog-2001
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// Description: The reset_controller module will safely reset a single stage
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// pipeline without using an asychronous reset (bleh). It is intended for use in
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// the TX engines, where it will control the output stage of the engine, and
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// provide a gracefull end-of-packet reset
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// Author: Dustin Richmond (@darichmond)
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//-----------------------------------------------------------------------------
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`define S_RC_IDLE 3'b001
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`define S_RC_WAIT 3'b010
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`define S_RC_ACTIVE 3'b100
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`include "trellis.vh"
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module reset_controller
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#(parameter C_RST_COUNT = 10)
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(
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input CLK,
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input RST_IN,
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output DONE_RST,
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output WAITING_RESET,
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output RST_OUT,
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input SIGNAL_RST,
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input WAIT_RST,
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input NEXT_CYC_RST);
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localparam C_CLOG2_RST_COUNT = clog2s(C_RST_COUNT);
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localparam C_CEIL2_RST_COUNT = 1 << C_CLOG2_RST_COUNT;
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reg [2:0] _rState,rState;
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wire [C_CLOG2_RST_COUNT:0] wRstCount;
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assign DONE_RST = rState[0];
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assign WAITING_RESET = rState[1] & NEXT_CYC_RST;
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assign RST_OUT = rState[2];
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counter
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#(// Parameters
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.C_MAX_VALUE (C_CEIL2_RST_COUNT),
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.C_SAT_VALUE (C_CEIL2_RST_COUNT),
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.C_RST_VALUE (C_CEIL2_RST_COUNT - C_RST_COUNT)
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/*AUTOINSTPARAM*/)
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rst_counter
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(// Outputs
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.VALUE (wRstCount),
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// Inputs
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.ENABLE (1'b1),
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.RST_IN (~rState[2] | RST_IN),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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always @(posedge CLK) begin
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if(RST_IN) begin
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rState <= `S_RC_ACTIVE;
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end else begin
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rState <= _rState;
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end
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end
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always @(*) begin
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_rState = rState;
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case(rState)
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`S_RC_IDLE:begin
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if(SIGNAL_RST & WAIT_RST) begin
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_rState = `S_RC_WAIT;
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end else if(SIGNAL_RST) begin
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_rState = `S_RC_ACTIVE;
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end
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end
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`S_RC_WAIT:begin
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if(NEXT_CYC_RST) begin
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_rState = `S_RC_ACTIVE;
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end
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end
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`S_RC_ACTIVE:begin
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if(wRstCount[C_CLOG2_RST_COUNT] & ~SIGNAL_RST) begin
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_rState = `S_RC_IDLE;
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end
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end
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default: _rState = rState;
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endcase
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end
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endmodule
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