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251 lines
8.0 KiB
Systemverilog
251 lines
8.0 KiB
Systemverilog
// ----------------------------------------------------------------------
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// Copyright (c) 2016, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Filename: tlp.vh
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// Version: 1.0
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// Verilog Standard: Verilog-2001
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// Description: The tlp.vh file is a header file that defines various
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// TLP specific primitives for the Xilinx and Altera "Classic" endpoints
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// Author: Dustin Richmond (@darichmond)
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//-----------------------------------------------------------------------------
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`ifndef __TLP_VH
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`define __TLP_VH 1
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`include "widths.vh"
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`include "types.vh"
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`define TLP_MAXHDR_W 128
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// Generic 1'st word TLP header widths & indices
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`define TLP_LEN_I 0
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`define TLP_LEN_W `LEN_W
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`define TLP_LEN_R `TLP_LEN_I +: `TLP_LEN_W
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`define TLP_ADDRTYPE_I 10
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`define TLP_ADDRTYPE_W 2
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`define TLP_ADDRTYPE_R `TLP_ADDRTYPE_I +: `TLP_ADDRTYPE_W
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`define TLP_ATTR0_I 12
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`define TLP_ATTR0_W 2
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`define TLP_ATTR0_R `TLP_ATTR0_I +: `TLP_ATTR0_W
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`define TLP_EP_I 14
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`define TLP_EP_W `EP_W
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`define TLP_EP_R `TLP_EP_I +: `TLP_EP_W
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`define TLP_TD_I 15
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`define TLP_TD_W `TD_W
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`define TLP_TD_R `TLP_TD_I +: `TLP_TD_W
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`define TLP_TH_I 16
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`define TLP_TH_W 1
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`define TLP_TH_R `TLP_TH_I +: `TLP_TH_W
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// Bit 17 is reserved
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`define TLP_RSVD0_I 17
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`define TLP_RSVD0_W 1
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`define TLP_RSVD0_R `TLP_RSVD0_I +: `TLP_RSVD0_W
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`define TLP_RSVD0_V `TLP_RSVD0_W'b0
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// There are two attr fields
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`define TLP_ATTR1_I 18
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`define TLP_ATTR1_W 1
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`define TLP_ATTR1_R `TLP_ATTR1_I +: `TLP_ATTR1_W
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`define TLP_ATTR_W (`TLP_ATTR0_W + `TLP_ATTR1_W)
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// Bit 19 is reserved
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`define TLP_RSVD1_I 19
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`define TLP_RSVD1_W 1
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`define TLP_RSVD1_R `TLP_RSVD1_I +: `TLP_RSVD1_W
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`define TLP_RSVD1_V `TLP_RSVD1_W'b0
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`define TLP_TC_I 20
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`define TLP_TC_W `TC_W
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`define TLP_TC_R `TLP_TC_I +: `TLP_TC_W
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// Bit 23 is reserved
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`define TLP_RSVD2_I 23
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`define TLP_RSVD2_W 1
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`define TLP_RSVD2_R `TLP_RSVD2_I +: `TLP_RSVD2_W
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`define TLP_RSVD2_V `TLP_RSVD2_W'b0
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`define TLP_TYPE_I 24
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`define TLP_TYPE_W `TYPE_W
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`define TLP_TYPE_R `TLP_TYPE_I +: `TLP_TYPE_W
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`define TLP_FMT_I 29
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`define TLP_FMT_W `FMT_W
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`define TLP_FMT_R `TLP_FMT_I +: `TLP_FMT_W
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`define TLP_4DWHBIT_I 29
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`define TLP_PAYBIT_I 30
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// Request specific fields
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`define TLP_REQMETADW0_I 0
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`define TLP_REQMETADW1_I 32
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`define TLP_REQADDRDW0_I 64
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`define TLP_REQADDRDW1_I 96
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`define TLP_REQFBE_I 32
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`define TLP_REQFBE_W `FBE_W
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`define TLP_REQFBE_R `TLP_REQFBE_I +: `TLP_REQFBE_W
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`define TLP_REQLBE_I 36
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`define TLP_REQLBE_W `LBE_W
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`define TLP_REQLBE_R `TLP_REQLBE_I +: `TLP_REQLBE_W
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`define TLP_REQTAG_I 40
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`define TLP_REQTAG_W `TAG_W
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`define TLP_REQTAG_R `TLP_REQTAG_I +: `TLP_REQTAG_W
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`define TLP_REQREQID_I 48
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`define TLP_REQREQID_W `REQID_W
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`define TLP_REQREQID_R `TLP_REQREQID_I +: `TLP_REQREQID_W
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`define TLP_REQADDRLO_I 64
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`define TLP_REQADDRLO_W 32
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`define TLP_REQADDRLO_R `TLP_REQADDRLO_I +: `TLP_REQADDRLO_W
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`define TLP_REQADDRHI_I 96
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`define TLP_REQADDRHI_W 32
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`define TLP_REQADDRHI_R `TLP_REQADDRHI_I +: `TLP_REQADDRHI_W
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`define TLP_REQADDR_W `ADDR_W
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// Completion specific fields
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`define TLP_CPLMETADW0_I 0
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`define TLP_CPLMETADW1_I 32
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`define TLP_CPLMETADW2_I 64
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`define TLP_CPLPAYLOAD_I 96
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`define TLP_CPLMDATA_I 95:0
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`define TLP_CPLHDR_W 96
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`define TLP_CPLBYTECNT_I 32
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`define TLP_CPLBYTECNT_W `BYTECNT_W
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`define TLP_CPLBYTECNT_R `TLP_CPLBYTECNT_I +: `TLP_CPLBYTECNT_W
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`define TLP_CPLBCM_I 44
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`define TLP_CPLBCM_W 1
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`define TLP_CPLBCM_R `TLP_CPLBCM_I +: `TLP_CPLBCM_W
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`define TLP_CPLSTAT_I 45
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`define TLP_CPLSTAT_W `STAT_W
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`define TLP_CPLSTAT_R `TLP_CPLSTAT_I +: `TLP_CPLSTAT_W
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`define TLP_CPLLEN_I 0
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`define TLP_CPLLEN_W `LEN_W
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`define TLP_CPLLEN_R `TLP_CPLLEN_I +: `TLP_CPLLEN_W
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`define TLP_CPLCPLID_I 48
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`define TLP_CPLCPLID_W `CPLID_W
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`define TLP_CPLCPLID_R `TLP_CPLCPLID_I +: `TLP_CPLCPLID_W
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`define TLP_CPLADDR_I 64
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`define TLP_CPLADDR_W `LOWADDR_W
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`define TLP_CPLADDR_R `TLP_CPLADDR_I +: `TLP_CPLADDR_W
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`define TLP_CPLRSVD0_I 71
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`define TLP_CPLRSVD0_W 1
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`define TLP_CPLRSVD0_R `TLP_CPLRSVD0_I +: `TLP_CPLRSVD0_W
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`define TLP_CPLTAG_I 72
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`define TLP_CPLTAG_W `TAG_W
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`define TLP_CPLTAG_R `TLP_CPLTAG_I +: `TLP_CPLTAG_W
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`define TLP_CPLREQID_I 80
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`define TLP_CPLREQID_W `REQID_W
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`define TLP_CPLREQID_R `TLP_CPLREQID_I +: `TLP_CPLREQID_W
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`define TLP_CPLFBE_W `FBE_W
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`define TLP_CPLLBE_W `LBE_W
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// Values
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`define TLP_4DWH_V 1'b1
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`define TLP_3DWH_V (~`TLP_4DWH_V)
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`define TLP_NODIGEST_V (`TLP_TD_W'b0)
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`define TLP_CPL_SUCCESSFUL_V `TLP_CPLSTAT_W'd0;
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// Decoding the format & Type field
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`define TLP_TYPE_REQ 5'b00000
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`define TLP_TYPE_CPL 5'b01010
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`define TLP_TYPE_MSG 5'b10001
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`define TLP_REQ_RD {{3'bx0x},`TLP_TYPE_REQ}
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`define TLP_REQ_WR {{3'bx1x},`TLP_TYPE_REQ}
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`define TLP_CPL_ND {{3'bx00},`TLP_TYPE_CPL}
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`define TLP_CPL_WD {{3'bx10},`TLP_TYPE_CPL}
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`define TLP_MSG_ND {{3'bx01},`TLP_TYPE_MSG}
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`define TLP_MSG_WD {{3'bx11},`TLP_TYPE_MSG}
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function [ `EXT_TYPE_W - 1 : 0 ] tlp_to_trellis_type;
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input [`FMT_W + `TYPE_W - 1 : 0 ] tlp_type;
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begin
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/* verilator lint_off CASEX */
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casex(tlp_type)
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`TLP_REQ_RD: tlp_to_trellis_type = `TRLS_REQ_RD;
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`TLP_REQ_WR: tlp_to_trellis_type = `TRLS_REQ_WR;
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`TLP_CPL_ND: tlp_to_trellis_type = `TRLS_CPL_ND;
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`TLP_CPL_WD: tlp_to_trellis_type = `TRLS_CPL_WD;
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`TLP_MSG_ND: tlp_to_trellis_type = `TRLS_MSG_ND; // We only use messages routed by address
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`TLP_MSG_WD: tlp_to_trellis_type = `TRLS_MSG_WD; // We only use messages routed by address
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default: tlp_to_trellis_type = `TRLS_REQ_RD;
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endcase
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/* verilator lint_on CASEX */
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end
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endfunction // if
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function [`FMT_W + `TYPE_W - 1 : 0 ] trellis_to_tlp_type;
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input [`EXT_TYPE_W - 1 : 0 ] trellis_type;
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input hdrlen_wr;
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reg [`FMT_W + `TYPE_W - 1 : 0 ] temp;
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begin
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/* verilator lint_off CASEX */
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casex(trellis_type)
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`TRLS_REQ_RD: temp = `TLP_REQ_RD;
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`TRLS_REQ_WR: temp = `TLP_REQ_WR;
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`TRLS_CPL_ND: temp = `TLP_CPL_ND;
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`TRLS_CPL_WD: temp = `TLP_CPL_WD;
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`TRLS_MSG_ND: temp = `TLP_MSG_ND; // We only use messages routed by address
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`TRLS_MSG_WD: temp = `TLP_MSG_WD; // We only use messages routed by address
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default: temp = `TLP_REQ_RD;
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endcase
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/* verilator lint_on CASEX */
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trellis_to_tlp_type = {temp[`FMT_W +`TYPE_W - 1 : `TYPE_W + 1], hdrlen_wr, temp[`TYPE_W-1:0]};
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end
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endfunction // if
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`endif
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