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188 lines
7.0 KiB
Verilog
188 lines
7.0 KiB
Verilog
// ----------------------------------------------------------------------
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// Copyright (c) 2015, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Filename: interrupt.v
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// Version: 1.00.a
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// Verilog Standard: Verilog-2001
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// Description: Manages the interrupt vector and sends interrupts.
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// Author: Matt Jacobsen
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// History: @mattj: Version 2.0
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//-----------------------------------------------------------------------------
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`define S_INTR_IDLE 2'd0
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`define S_INTR_INTR 2'd1
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`define S_INTR_CLR_0 2'd2
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`define S_INTR_CLR_1 2'd3
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`timescale 1ns/1ns
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module interrupt #(
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parameter C_NUM_CHNL = 4'd12
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)
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(
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input CLK,
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input RST,
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input [C_NUM_CHNL-1:0] RX_SG_BUF_RECVD, // The scatter gather data for a rx_port transaction has been read
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input [C_NUM_CHNL-1:0] RX_TXN_DONE, // The rx_port transaction is done
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input [C_NUM_CHNL-1:0] TX_TXN, // New tx_port transaction
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input [C_NUM_CHNL-1:0] TX_SG_BUF_RECVD, // The scatter gather data for a tx_port transaction has been read
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input [C_NUM_CHNL-1:0] TX_TXN_DONE, // The tx_port transaction is done
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input VECT_0_RST, // Interrupt vector 0 reset
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input VECT_1_RST, // Interrupt vector 1 reset
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input [31:0] VECT_RST, // Interrupt vector reset value
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output [31:0] VECT_0, // Interrupt vector 0
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output [31:0] VECT_1, // Interrupt vector 1
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input INTR_LEGACY_CLR, // Pulsed high to ack the legacy interrupt and clear it
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input CONFIG_INTERRUPT_MSIENABLE, // 1 if MSI interrupts are enable, 0 if only legacy are supported
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input INTR_MSI_RDY, // High when interrupt is able to be sent
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output INTR_MSI_REQUEST // High to request interrupt, when both INTR_MSI_RDY and INTR_MSI_REQUEST are high, interrupt is sent
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);
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reg [1:0] rState=0;
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reg [31:0] rVect0=0;
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reg [31:0] rVect1=0;
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wire [31:0] wVect0;
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wire [31:0] wVect1;
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wire wIntr = (rState == `S_INTR_INTR);
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wire wIntrDone;
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assign VECT_0 = rVect0;
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assign VECT_1 = rVect1;
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// Align the input signals to the interrupt vector.
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// VECT_0/VECT_1 are organized from right to left (LSB to MSB) as:
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// [ 0] TX_TXN for channel 0 in VECT_0, channel 6 in VECT_1
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// [ 1] TX_SG_BUF_RECVD for channel 0 in VECT_0, channel 6 in VECT_1
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// [ 2] TX_TXN_DONE for channel 0 in VECT_0, channel 6 in VECT_1
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// [ 3] RX_SG_BUF_RECVD for channel 0 in VECT_0, channel 6 in VECT_1
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// [ 4] RX_TXN_DONE for channel 0 in VECT_0, channel 6 in VECT_1
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// ...
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// [25] TX_TXN for channel 5 in VECT_0, channel 11 in VECT_1
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// [26] TX_SG_BUF_RECVD for channel 5 in VECT_0, channel 11 in VECT_1
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// [27] TX_TXN_DONE for channel 5 in VECT_0, channel 11 in VECT_1
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// [28] RX_SG_BUF_RECVD for channel 5 in VECT_0, channel 11 in VECT_1
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// [29] RX_TXN_DONE for channel 5 in VECT_0, channel 11 in VECT_1
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// Positions 30 - 31 in both VECT_0 and VECT_1 are zero.
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genvar i;
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generate
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for (i = 0; i < C_NUM_CHNL; i = i + 1) begin: vectMap
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if (i < 6) begin : vectMap0
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assign wVect0[(5*i)+0] = TX_TXN[i];
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assign wVect0[(5*i)+1] = TX_SG_BUF_RECVD[i];
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assign wVect0[(5*i)+2] = TX_TXN_DONE[i];
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assign wVect0[(5*i)+3] = RX_SG_BUF_RECVD[i];
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assign wVect0[(5*i)+4] = RX_TXN_DONE[i];
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end
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else begin : vectMap1
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assign wVect1[(5*(i-6))+0] = TX_TXN[i];
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assign wVect1[(5*(i-6))+1] = TX_SG_BUF_RECVD[i];
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assign wVect1[(5*(i-6))+2] = TX_TXN_DONE[i];
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assign wVect1[(5*(i-6))+3] = RX_SG_BUF_RECVD[i];
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assign wVect1[(5*(i-6))+4] = RX_TXN_DONE[i];
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end
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end
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for (i = C_NUM_CHNL; i < 12; i = i + 1) begin: vectZero
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if (i < 6) begin : vectZero0
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assign wVect0[(5*i)+0] = 1'b0;
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assign wVect0[(5*i)+1] = 1'b0;
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assign wVect0[(5*i)+2] = 1'b0;
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assign wVect0[(5*i)+3] = 1'b0;
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assign wVect0[(5*i)+4] = 1'b0;
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end
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else begin : vectZero1
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assign wVect1[(5*(i-6))+0] = 1'b0;
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assign wVect1[(5*(i-6))+1] = 1'b0;
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assign wVect1[(5*(i-6))+2] = 1'b0;
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assign wVect1[(5*(i-6))+3] = 1'b0;
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assign wVect1[(5*(i-6))+4] = 1'b0;
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end
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end
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assign wVect0[30] = 1'b0;
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assign wVect0[31] = 1'b0;
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assign wVect1[30] = 1'b0;
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assign wVect1[31] = 1'b0;
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endgenerate
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// Interrupt controller
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interrupt_controller intrCtlr (
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.CLK(CLK),
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.RST(RST),
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.INTR(wIntr),
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.INTR_LEGACY_CLR(INTR_LEGACY_CLR),
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.INTR_DONE(wIntrDone),
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.CFG_INTERRUPT_ASSERT(),
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.CONFIG_INTERRUPT_MSIENABLE(CONFIG_INTERRUPT_MSIENABLE),
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.INTR_MSI_RDY(INTR_MSI_RDY),
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.INTR_MSI_REQUEST(INTR_MSI_REQUEST)
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);
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// Update the interrupt vector when new signals come in (pulse in) and on reset.
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always @(posedge CLK) begin
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if (RST) begin
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rVect0 <= #1 0;
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rVect1 <= #1 0;
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end
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else begin
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if (VECT_0_RST) begin
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rVect0 <= #1 (wVect0 | (rVect0 & ~VECT_RST));
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rVect1 <= #1 (wVect1 | rVect1);
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end
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else if (VECT_1_RST) begin
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rVect0 <= #1 (wVect0 | rVect0);
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rVect1 <= #1 (wVect1 | (rVect1 & ~VECT_RST));
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end
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else begin
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rVect0 <= #1 (wVect0 | rVect0);
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rVect1 <= #1 (wVect1 | rVect1);
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end
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end
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end
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// Fire the interrupt when we have a non-zero vector.
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always @(posedge CLK) begin
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if (RST) begin
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rState <= #1 `S_INTR_IDLE;
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end
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else begin
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case (rState)
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`S_INTR_IDLE : rState <= #1 ((rVect0 | rVect1) == 0 ? `S_INTR_IDLE : `S_INTR_INTR);
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`S_INTR_INTR : rState <= #1 (wIntrDone ? `S_INTR_CLR_0 : `S_INTR_INTR);
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`S_INTR_CLR_0 : rState <= #1 (VECT_0_RST ? (C_NUM_CHNL > 6 ? `S_INTR_CLR_1 : `S_INTR_IDLE) : `S_INTR_CLR_0);
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`S_INTR_CLR_1 : rState <= #1 (VECT_1_RST ? `S_INTR_IDLE : `S_INTR_CLR_1);
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endcase
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end
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end
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endmodule
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