mirror of
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348 lines
16 KiB
Verilog
348 lines
16 KiB
Verilog
// ----------------------------------------------------------------------
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// Copyright (c) 2015, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Filename: txc_engine_classic.v
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// Version: 1.0
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// Verilog Standard: Verilog-2001
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// Description: The TXC Engine takes unformatted completions, formats
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// these packets into "TLP's" or Transaction Layer Packets. These
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// packets must meet max-request, max-payload, and payload termination
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// requirements (see Read Completion Boundary). The TXC Engine does not
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// check these requirements during operation, but may do so during
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// simulation.
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// This file also contains the txc_formatter module, which formats
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// completion headers.
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// Author: Dustin Richmond (@darichmond)
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//-----------------------------------------------------------------------------
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`timescale 1ns/1ns
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`include "trellis.vh" // Defines the user-facing signal widths.
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`include "tlp.vh" // Defines the endpoint-facing field widths in a TLP
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module txc_engine_classic
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#(parameter C_PCI_DATA_WIDTH = 128,
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parameter C_PIPELINE_INPUT = 1,
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parameter C_PIPELINE_OUTPUT = 0,
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parameter C_MAX_PAYLOAD_DWORDS = 64,
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parameter C_DEPTH_PACKETS = 10,
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parameter C_VENDOR = "ALTERA")
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(// Interface: Clocks
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input CLK,
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// Interface: Resets
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input RST_IN, // Addition for RIFFA_RST
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output DONE_TXC_RST,
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// Interface: Configuration
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input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
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// Interface: TXC Classic
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input TXC_TLP_READY,
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output [C_PCI_DATA_WIDTH-1:0] TXC_TLP,
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output TXC_TLP_VALID,
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output TXC_TLP_START_FLAG,
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output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_TLP_START_OFFSET,
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output TXC_TLP_END_FLAG,
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output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_TLP_END_OFFSET,
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// Interface: TXC Engine
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input TXC_DATA_VALID,
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input [C_PCI_DATA_WIDTH-1:0] TXC_DATA,
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input TXC_DATA_START_FLAG,
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input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_START_OFFSET,
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input TXC_DATA_END_FLAG,
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input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_END_OFFSET,
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output TXC_DATA_READY,
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input TXC_META_VALID,
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input [`SIG_FBE_W-1:0] TXC_META_FDWBE,
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input [`SIG_LBE_W-1:0] TXC_META_LDWBE,
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input [`SIG_LOWADDR_W-1:0] TXC_META_ADDR,
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input [`SIG_TYPE_W-1:0] TXC_META_TYPE,
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input [`SIG_LEN_W-1:0] TXC_META_LENGTH,
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input [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT,
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input [`SIG_TAG_W-1:0] TXC_META_TAG,
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input [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID,
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input [`SIG_TC_W-1:0] TXC_META_TC,
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input [`SIG_ATTR_W-1:0] TXC_META_ATTR,
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input TXC_META_EP,
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output TXC_META_READY);
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localparam C_DATA_WIDTH = C_PCI_DATA_WIDTH;
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localparam C_MAX_HDR_WIDTH = `TLP_MAXHDR_W;
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localparam C_MAX_ALIGN_WIDTH = (C_VENDOR == "ALTERA") ? 32:
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(C_VENDOR == "XILINX") ? 0 :
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0;
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localparam C_PIPELINE_FORMATTER_INPUT = C_PIPELINE_INPUT;
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localparam C_PIPELINE_FORMATTER_OUTPUT = C_PIPELINE_OUTPUT;
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localparam C_FORMATTER_DELAY = C_PIPELINE_FORMATTER_OUTPUT + C_PIPELINE_FORMATTER_INPUT;
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/*AUTOWIRE*/
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/*AUTOINPUT*/
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///*AUTOOUTPUT*/
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wire wTxHdrReady;
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wire wTxHdrValid;
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wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
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wire [`SIG_TYPE_W-1:0] wTxType;
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wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
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wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
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wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
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wire wTxHdrNopayload;
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assign DONE_TXC_RST = ~RST_IN;
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txc_formatter_classic
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#(
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.C_PIPELINE_OUTPUT (C_PIPELINE_FORMATTER_OUTPUT),
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.C_PIPELINE_INPUT (C_PIPELINE_FORMATTER_INPUT),
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/*AUTOINSTPARAM*/
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// Parameters
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.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
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.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
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.C_MAX_ALIGN_WIDTH (C_MAX_ALIGN_WIDTH),
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.C_VENDOR (C_VENDOR))
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txc_formatter_inst
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(
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// Outputs
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.TX_HDR_VALID (wTxHdrValid),
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.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
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.TX_HDR_NOPAYLOAD (wTxHdrNopayload),
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.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
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.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
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.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
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// Inputs
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.TX_HDR_READY (wTxHdrReady),
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/*AUTOINST*/
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// Outputs
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.TXC_META_READY (TXC_META_READY),
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN),
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.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
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.TXC_META_VALID (TXC_META_VALID),
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.TXC_META_FDWBE (TXC_META_FDWBE[`SIG_FBE_W-1:0]),
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.TXC_META_LDWBE (TXC_META_LDWBE[`SIG_LBE_W-1:0]),
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.TXC_META_ADDR (TXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
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.TXC_META_LENGTH (TXC_META_LENGTH[`SIG_LEN_W-1:0]),
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.TXC_META_BYTE_COUNT (TXC_META_BYTE_COUNT[`SIG_BYTECNT_W-1:0]),
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.TXC_META_TAG (TXC_META_TAG[`SIG_TAG_W-1:0]),
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.TXC_META_TYPE (TXC_META_TYPE[`SIG_TYPE_W-1:0]),
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.TXC_META_REQUESTER_ID (TXC_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
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.TXC_META_TC (TXC_META_TC[`SIG_TC_W-1:0]),
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.TXC_META_ATTR (TXC_META_ATTR[`SIG_ATTR_W-1:0]),
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.TXC_META_EP (TXC_META_EP));
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tx_engine
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#(
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.C_DATA_WIDTH (C_PCI_DATA_WIDTH),
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/*AUTOINSTPARAM*/
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// Parameters
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.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
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.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
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.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
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.C_FORMATTER_DELAY (C_FORMATTER_DELAY),
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.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
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.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS),
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.C_VENDOR (C_VENDOR))
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txc_engine_inst
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(
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// Outputs
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.TX_HDR_READY (wTxHdrReady),
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.TX_DATA_READY (TXC_DATA_READY),
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.TX_PKT (TXC_TLP[C_DATA_WIDTH-1:0]),
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.TX_PKT_START_FLAG (TXC_TLP_START_FLAG),
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.TX_PKT_START_OFFSET (TXC_TLP_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
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.TX_PKT_END_FLAG (TXC_TLP_END_FLAG),
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.TX_PKT_END_OFFSET (TXC_TLP_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
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.TX_PKT_VALID (TXC_TLP_VALID),
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// Inputs
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.TX_HDR_VALID (wTxHdrValid),
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.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
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.TX_HDR_NOPAYLOAD (wTxHdrNopayload),
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.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
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.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
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.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
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.TX_DATA_VALID (TXC_DATA_VALID),
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.TX_DATA (TXC_DATA[C_DATA_WIDTH-1:0]),
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.TX_DATA_START_FLAG (TXC_DATA_START_FLAG),
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.TX_DATA_START_OFFSET (TXC_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
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.TX_DATA_END_FLAG (TXC_DATA_END_FLAG),
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.TX_DATA_END_OFFSET (TXC_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
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.TX_PKT_READY (TXC_TLP_READY),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN));
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endmodule
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module txc_formatter_classic
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#(
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parameter C_PCI_DATA_WIDTH = 10'd128,
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parameter C_MAX_HDR_WIDTH = `TLP_MAXHDR_W,
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parameter C_MAX_ALIGN_WIDTH = 32,
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parameter C_PIPELINE_INPUT = 1,
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parameter C_PIPELINE_OUTPUT = 1,
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parameter C_VENDOR = "ALTERA"
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)
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(
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// Interface: Clocks
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input CLK,
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// Interface: Resets
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input RST_IN,
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// Interface: Configuration
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input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
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// Interface: TXC
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input TXC_META_VALID,
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input [`SIG_FBE_W-1:0] TXC_META_FDWBE,
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input [`SIG_LBE_W-1:0] TXC_META_LDWBE,
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input [`SIG_LOWADDR_W-1:0] TXC_META_ADDR,
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input [`SIG_LEN_W-1:0] TXC_META_LENGTH,
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input [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT,
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input [`SIG_TAG_W-1:0] TXC_META_TAG,
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input [`SIG_TYPE_W-1:0] TXC_META_TYPE,
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input [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID,
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input [`SIG_TC_W-1:0] TXC_META_TC,
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input [`SIG_ATTR_W-1:0] TXC_META_ATTR,
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input TXC_META_EP,
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output TXC_META_READY,
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// Interface: TX HDR
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output TX_HDR_VALID,
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output [C_MAX_HDR_WIDTH-1:0] TX_HDR,
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output [`SIG_LEN_W-1:0] TX_HDR_PAYLOAD_LEN,
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output [`SIG_NONPAY_W-1:0] TX_HDR_NONPAY_LEN,
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output [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,
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output TX_HDR_NOPAYLOAD,
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input TX_HDR_READY
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);
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wire [C_MAX_HDR_WIDTH-1:0] wCplHdr;
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wire wTxHdrReady;
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wire wTxHdrValid;
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wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
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wire [`SIG_TYPE_W-1:0] wTxType;
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wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
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wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
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wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
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wire wTxHdrNopayload;
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wire [`TLP_CPLADDR_W-1:0] wTxLoAddr;
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// Reserved Fields
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assign wCplHdr[`TLP_RSVD0_R] = `TLP_RSVD0_V;
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assign wCplHdr[`TLP_ADDRTYPE_R] = `TLP_ADDRTYPE_W'b0;
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assign wCplHdr[`TLP_TH_R] = `TLP_TH_W'b0;
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assign wCplHdr[`TLP_RSVD1_R] = `TLP_RSVD1_V;
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assign wCplHdr[`TLP_RSVD2_R] = `TLP_RSVD2_V;
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assign wCplHdr[`TLP_CPLBCM_R] = `TLP_CPLBCM_W'b0;
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assign wCplHdr[`TLP_CPLRSVD0_R] = `TLP_CPLRSVD0_W'b0;
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assign wCplHdr[127:96] = 32'b0;
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// Generic Header Fields
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assign wCplHdr[`TLP_LEN_R] = TXC_META_LENGTH;
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assign wCplHdr[`TLP_EP_R] = TXC_META_EP;
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assign wCplHdr[`TLP_TD_R] = `TLP_NODIGEST_V;
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assign wCplHdr[`TLP_ATTR0_R] = TXC_META_ATTR[1:0];
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assign wCplHdr[`TLP_ATTR1_R] = TXC_META_ATTR[2];
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assign {wCplHdr[`TLP_FMT_R], wCplHdr[`TLP_TYPE_R]} = trellis_to_tlp_type(TXC_META_TYPE,0);
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assign wCplHdr[`TLP_TC_R] = TXC_META_TC;
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// Completion Specific Fields
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assign wCplHdr[`TLP_CPLBYTECNT_R] = TXC_META_BYTE_COUNT;
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assign wCplHdr[`TLP_CPLSTAT_R] = 0;
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assign wCplHdr[`TLP_CPLCPLID_R] = CONFIG_COMPLETER_ID;
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assign wCplHdr[`TLP_CPLADDR_R] = TXC_META_ADDR;
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assign wCplHdr[`TLP_CPLTAG_R] = TXC_META_TAG;
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assign wCplHdr[`TLP_CPLREQID_R] = TXC_META_REQUESTER_ID;
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// Metadata, to the aligner
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assign wTxLoAddr = wTxHdr[`TLP_CPLADDR_R];
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assign wTxHdrNopayload = ~wTxHdr[`TLP_PAYBIT_I];
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assign wTxHdrNonpayLen = 3 + ((C_VENDOR == "ALTERA")? {3'b0,(~wTxLoAddr[2] & ~wTxHdrNopayload)} : 4'b0);
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assign wTxHdrPayloadLen = wTxHdrNopayload ? 0 : wTxHdr[`TLP_LEN_R];
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assign wTxHdrPacketLen = wTxHdrPayloadLen + wTxHdrNonpayLen;
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pipeline
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#(// Parameters
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.C_DEPTH (C_PIPELINE_INPUT?1:0),
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.C_WIDTH (C_MAX_HDR_WIDTH),
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.C_USE_MEMORY (0)
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/*AUTOINSTPARAM*/)
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input_inst
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(// Outputs
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.WR_DATA_READY (TXC_META_READY),
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.RD_DATA (wTxHdr),
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.RD_DATA_VALID (wTxHdrValid),
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// Inputs
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.WR_DATA (wCplHdr),
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.WR_DATA_VALID (TXC_META_VALID),
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.RD_DATA_READY (wTxHdrReady),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN));
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pipeline
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#(
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// Parameters
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.C_DEPTH (C_PIPELINE_OUTPUT?1:0),
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.C_WIDTH (C_MAX_HDR_WIDTH+ 1 + `SIG_PACKETLEN_W + `SIG_LEN_W + `SIG_NONPAY_W),
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.C_USE_MEMORY (0)
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/*AUTOINSTPARAM*/)
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output_inst
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(
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// Outputs
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.WR_DATA_READY (wTxHdrReady),
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.RD_DATA ({TX_HDR,TX_HDR_NOPAYLOAD,TX_HDR_PACKET_LEN,TX_HDR_PAYLOAD_LEN,TX_HDR_NONPAY_LEN}),
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.RD_DATA_VALID (TX_HDR_VALID),
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// Inputs
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.WR_DATA ({wTxHdr,wTxHdrNopayload,wTxHdrPacketLen,wTxHdrPayloadLen,wTxHdrNonpayLen}),
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.WR_DATA_VALID (wTxHdrValid),
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.RD_DATA_READY (TX_HDR_READY),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN));
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endmodule
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// Local Variables:
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// verilog-library-directories:("." "../../../common/" "../../common/")
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// End:
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