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38 lines
615 B
Systemverilog
38 lines
615 B
Systemverilog
`ifndef __WIDTHS_VH
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`define __WIDTHS_VH 1
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`define LEN_W 10
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`define TD_W 1
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`define BARDECODE_W 8
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`define OFFSET_W 4
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`define EP_W 1
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`define TC_W 3
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`define TYPE_W 5
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`define ATTR_W 3
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`define FMT_W 3
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`define FBE_W 4
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`define LBE_W 4
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`define TAG_W 8
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`define ADDR_W 64
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`define REQID_W 16
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`define CPLID_W 16
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`define BYTECNT_W 12
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`define STAT_W 3
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`define LOWADDR_W 7
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`define EXT_TYPE_W 3
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`define LINKWIDTH_W 6
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`define LINKRATE_W 4
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`define MAXREAD_W 3
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`define MAXPAYLOAD_W 3
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`define PCIE_CONFIGURATION_REGISTER_WIDTH 16
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`define PCIE_BUS_ID_WIDTH 8
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`define PCIE_DEVICE_ID_WIDTH 5
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`define PCIE_FUNCTION_ID_WIDTH 3
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`endif
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