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246 lines
10 KiB
Verilog
246 lines
10 KiB
Verilog
// ----------------------------------------------------------------------
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// Copyright (c) 2015, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Filename: tx_data_pipeline.v
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// Version: 1.0
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// Verilog Standard: Verilog-2001
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//
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// Description: The tx_data_fifo takes 0-bit aligned packet data and
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// puts each DW into one of N FIFOs where N = (C_DATA_WIDTH/32).
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//
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// The data interface (TX_DATA) is an interface for N 32-bit FIFOs, where N =
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// (C_DATA_WIDTH/32). The START_FLAG signal indicates that the first dword of
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// a packet is in FIFO 0 (TX_DATA[31:0]). Each FIFO interface also contains an
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// END_FLAG signal in the END_FLAGS bus. When a bit in END_FLAGS bus is asserted,
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// its corresponding fifo contains the last dword of data for the current
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// packet. START_FLAG, END_FLAG and DATA are all qualified by the VALID signal,
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// and read by the READY signal.
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//
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// The write interface (WR_TX) differs slightly from the read interface because it
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// produces a READY signal and consumes a VALID signal. VALID is asserted when an
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// entire packet has been packed into a FIFO.
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//
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// TODO:
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// - Make sure that the synthesis tool is removing the other three start
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// flag wires (and modifying the width of the FIFOs)
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//
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// Author: Dustin Richmond (@darichmond)
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//-----------------------------------------------------------------------------
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`timescale 1ns/1ns
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`include "trellis.vh" // Defines the user-facing signal widths.
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module tx_data_fifo
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#(parameter C_DEPTH_PACKETS = 10,
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parameter C_DATA_WIDTH = 128,
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parameter C_PIPELINE_INPUT = 1,
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parameter C_PIPELINE_OUTPUT = 1,
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parameter C_MAX_PAYLOAD = 256 // BYTES
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)
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(
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// Interface: Clocks
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input CLK,
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// Interface: Reset
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input RST_IN,
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// Interface: WR TX DATA
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input [C_DATA_WIDTH-1:0] WR_TX_DATA,
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input WR_TX_DATA_VALID,
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input WR_TX_DATA_START_FLAG,
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input [(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_WORD_VALID,
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input [(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_END_FLAGS,
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output WR_TX_DATA_READY,
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// Interface: RD TX DATA
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input [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_WORD_READY,
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output [C_DATA_WIDTH-1:0] RD_TX_DATA,
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output RD_TX_DATA_START_FLAG,
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output [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_END_FLAGS,
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output [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_WORD_VALID,
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output RD_TX_DATA_PACKET_VALID
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);
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localparam C_FIFO_OUTPUT_DEPTH = 1;
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localparam C_INPUT_DEPTH = C_PIPELINE_INPUT != 0 ? 1 : 0;
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localparam C_OUTPUT_DEPTH = C_PIPELINE_OUTPUT != 0 ? 1 : 0;
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localparam C_MAXPACKET_LINES = (C_MAX_PAYLOAD*8)/C_DATA_WIDTH;
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localparam C_FIFO_DEPTH = C_MAXPACKET_LINES*C_DEPTH_PACKETS;
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localparam C_FIFO_DATA_WIDTH = 32;
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localparam C_REGISTER_WIDTH = C_FIFO_DATA_WIDTH + 2;
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localparam C_FIFO_WIDTH = C_FIFO_DATA_WIDTH + 2; // Data, end flag and start flag
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localparam C_NUM_FIFOS = (C_DATA_WIDTH/32);
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genvar i;
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wire RST;
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wire [C_FIFO_DATA_WIDTH-1:0] wWrTxData[C_NUM_FIFOS-1:0];
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wire [C_NUM_FIFOS-1:0] wWrTxDataValid;
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wire [C_NUM_FIFOS-1:0] wWrTxDataReady;
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wire [C_NUM_FIFOS-1:0] wWrTxDataStartFlags;
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wire [C_NUM_FIFOS-1:0] wWrTxDataEndFlags;
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wire [C_NUM_FIFOS-1:0] _wRdTxDataStartFlags;
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wire [C_FIFO_DATA_WIDTH-1:0] wRdTxData[C_NUM_FIFOS-1:0];
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wire [C_NUM_FIFOS-1:0] wRdTxDataValid;
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wire [C_NUM_FIFOS-1:0] wRdTxDataReady;
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wire [C_NUM_FIFOS-1:0] wRdTxDataStartFlags;
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wire [C_NUM_FIFOS-1:0] wRdTxDataEndFlags;
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wire wRdTxDataPacketValid;
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wire wWrTxEndFlagValid;
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wire wWrTxEndFlagReady;
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wire wRdTxEndFlagValid;
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wire wRdTxEndFlagReady;
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wire wPacketDecrement;
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wire wPacketIncrement;
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reg [clog2(C_DEPTH_PACKETS+1)-1:0] rPacketCounter,_rPacketCounter;
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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///*AUTOOUTPUT*/
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assign RST = RST_IN;
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assign wWrTxEndFlagValid = (wWrTxDataEndFlags & wWrTxDataValid) != {C_NUM_FIFOS{1'b0}};
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assign wWrTxEndFlagReady = rPacketCounter != C_DEPTH_PACKETS;// Designed a small bit of latency here to help timing...
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assign wPacketIncrement = wWrTxEndFlagValid & wWrTxEndFlagReady;
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assign wPacketDecrement = wRdTxEndFlagValid & wRdTxEndFlagReady;
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assign WR_TX_DATA_READY = wWrTxEndFlagReady;
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assign wRdTxEndFlagValid = rPacketCounter != 0;
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assign wRdTxEndFlagReady = (wRdTxDataReady & wRdTxDataEndFlags & wRdTxDataValid) != {C_NUM_FIFOS{1'b0}};
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assign wRdTxDataPacketValid = rPacketCounter != 0;
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assign RD_TX_DATA_START_FLAG = _wRdTxDataStartFlags[0];
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always @(*) begin
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_rPacketCounter = rPacketCounter;
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if(wPacketIncrement & wPacketDecrement) begin
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_rPacketCounter = rPacketCounter + 0;
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end else if(wPacketIncrement) begin
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_rPacketCounter = rPacketCounter + 1;
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end else if(wPacketDecrement) begin
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_rPacketCounter = rPacketCounter - 1;
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end
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end // always @ (*)
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always @(posedge CLK) begin
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if(RST_IN) begin
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rPacketCounter <= #1 0;
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end else begin
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rPacketCounter <= #1 _rPacketCounter;
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end
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end
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generate
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for( i = 0 ; i < C_NUM_FIFOS ; i = i + 1 ) begin : gen_regs_fifos
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pipeline
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#(
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.C_DEPTH (C_INPUT_DEPTH),
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.C_USE_MEMORY (0),
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.C_WIDTH (C_REGISTER_WIDTH)
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/*AUTOINSTPARAM*/)
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input_pipeline_inst_
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(
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// Outputs
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.WR_DATA_READY (),
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.RD_DATA ({wWrTxData[i], wWrTxDataEndFlags[i],wWrTxDataStartFlags[i]}),
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.RD_DATA_VALID (wWrTxDataValid[i]),
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN),
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.WR_DATA ({WR_TX_DATA[C_FIFO_DATA_WIDTH*i +: C_FIFO_DATA_WIDTH],
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WR_TX_DATA_END_FLAGS[i], (i == 0) ? WR_TX_DATA_START_FLAG: 1'b0}),
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.WR_DATA_VALID (WR_TX_DATA_VALID & WR_TX_DATA_WORD_VALID[i]),
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.RD_DATA_READY (wWrTxDataReady[i]));
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fifo
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#(
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// Parameters
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.C_WIDTH (C_FIFO_WIDTH),
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.C_DEPTH (C_FIFO_DEPTH),
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.C_DELAY (0)
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/*AUTOINSTPARAM*/)
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fifo_inst_
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(
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// Outputs
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.RD_DATA ({wRdTxData[i], wRdTxDataStartFlags[i], wRdTxDataEndFlags[i]}),
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.WR_READY (wWrTxDataReady[i]),
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.RD_VALID (wRdTxDataValid[i]),
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// Inputs
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.WR_DATA ({wWrTxData[i], wWrTxDataStartFlags[i], wWrTxDataEndFlags[i]}),
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.WR_VALID (wWrTxDataValid[i]),
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.RD_READY (wRdTxDataReady[i]),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK),
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.RST (RST));
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pipeline
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#(
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.C_DEPTH (C_FIFO_OUTPUT_DEPTH),
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.C_USE_MEMORY (0),
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.C_WIDTH (C_FIFO_WIDTH)
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/*AUTOINSTPARAM*/)
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fifo_pipeline_inst_
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(
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// Outputs
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.WR_DATA_READY (wRdTxDataReady[i]),
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.RD_DATA ({RD_TX_DATA[i*32 +: 32],
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_wRdTxDataStartFlags[i],
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RD_TX_DATA_END_FLAGS[i]}),
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.RD_DATA_VALID (RD_TX_DATA_WORD_VALID[i]),
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// Inputs
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.WR_DATA ({wRdTxData[i],
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wRdTxDataStartFlags[i],
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wRdTxDataEndFlags[i]}),
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.WR_DATA_VALID (wRdTxDataValid[i]),
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.RD_DATA_READY (RD_TX_DATA_WORD_READY[i]),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN));
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end // for ( i = 0 ; i < C_NUM_FIFOS ; i = i + 1 )
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endgenerate
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endmodule
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// Local Variables:
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// verilog-library-directories:("." "../../common/")
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// End:
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