mirror of
https://github.com/KastnerRG/riffa.git
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516 lines
16 KiB
Verilog
516 lines
16 KiB
Verilog
// ----------------------------------------------------------------------
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// Copyright (c) 2016, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Filename: rx_port_128.v
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// Version: 1.00.a
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// Verilog Standard: Verilog-2001
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// Description: Receives data from the rx_engine and buffers the output
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// for the RIFFA channel.
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// Author: Matt Jacobsen
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// History: @mattj: Version 2.0
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//-----------------------------------------------------------------------------
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`timescale 1ns/1ns
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module rx_port_128 #(
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parameter C_DATA_WIDTH = 9'd128,
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parameter C_MAIN_FIFO_DEPTH = 1024,
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parameter C_SG_FIFO_DEPTH = 512,
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parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
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// Local parameters
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parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1),
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parameter C_MAIN_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_MAIN_FIFO_DEPTH))+1),
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parameter C_SG_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_SG_FIFO_DEPTH))+1)
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)
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(
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input CLK,
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input RST,
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input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
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output SG_RX_BUF_RECVD, // Scatter gather RX buffer completely read (ready for next if applicable)
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input [31:0] SG_RX_BUF_DATA, // Scatter gather RX buffer data
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input SG_RX_BUF_LEN_VALID, // Scatter gather RX buffer length valid
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input SG_RX_BUF_ADDR_HI_VALID, // Scatter gather RX buffer high address valid
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input SG_RX_BUF_ADDR_LO_VALID, // Scatter gather RX buffer low address valid
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output SG_TX_BUF_RECVD, // Scatter gather TX buffer completely read (ready for next if applicable)
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input [31:0] SG_TX_BUF_DATA, // Scatter gather TX buffer data
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input SG_TX_BUF_LEN_VALID, // Scatter gather TX buffer length valid
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input SG_TX_BUF_ADDR_HI_VALID, // Scatter gather TX buffer high address valid
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input SG_TX_BUF_ADDR_LO_VALID, // Scatter gather TX buffer low address valid
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output [C_DATA_WIDTH-1:0] SG_DATA, // Scatter gather TX buffer data
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output SG_DATA_EMPTY, // Scatter gather TX buffer data empty
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input SG_DATA_REN, // Scatter gather TX buffer data read enable
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input SG_RST, // Scatter gather TX buffer data reset
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output SG_ERR, // Scatter gather TX encountered an error
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input [31:0] TXN_DATA, // Read transaction data
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input TXN_LEN_VALID, // Read transaction length valid
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input TXN_OFF_LAST_VALID, // Read transaction offset/last valid
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output [31:0] TXN_DONE_LEN, // Read transaction actual transfer length
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output TXN_DONE, // Read transaction done
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input TXN_DONE_ACK, // Read transaction actual transfer length read
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output RX_REQ, // Read request
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input RX_REQ_ACK, // Read request accepted
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output [1:0] RX_REQ_TAG, // Read request data tag
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output [63:0] RX_REQ_ADDR, // Read request address
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output [9:0] RX_REQ_LEN, // Read request length
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input [C_DATA_WIDTH-1:0] MAIN_DATA, // Main incoming data
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input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN, // Main incoming data enable
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input MAIN_DONE, // Main incoming data complete
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input MAIN_ERR, // Main incoming data completed with error
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input [C_DATA_WIDTH-1:0] SG_RX_DATA, // Scatter gather for RX incoming data
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input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN, // Scatter gather for RX incoming data enable
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input SG_RX_DONE, // Scatter gather for RX incoming data complete
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input SG_RX_ERR, // Scatter gather for RX incoming data completed with error
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input [C_DATA_WIDTH-1:0] SG_TX_DATA, // Scatter gather for TX incoming data
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input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN, // Scatter gather for TX incoming data enable
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input SG_TX_DONE, // Scatter gather for TX incoming data complete
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input SG_TX_ERR, // Scatter gather for TX incoming data completed with error
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input CHNL_CLK, // Channel read clock
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output CHNL_RX, // Channel read receive signal
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input CHNL_RX_ACK, // Channle read received signal
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output CHNL_RX_LAST, // Channel last read
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output [31:0] CHNL_RX_LEN, // Channel read length
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output [30:0] CHNL_RX_OFF, // Channel read offset
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output [C_DATA_WIDTH-1:0] CHNL_RX_DATA, // Channel read data
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output CHNL_RX_DATA_VALID, // Channel read data valid
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input CHNL_RX_DATA_REN // Channel read data has been recieved
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);
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`include "functions.vh"
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wire [C_DATA_WIDTH-1:0] wPackedMainData;
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wire wPackedMainWen;
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wire wPackedMainDone;
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wire wPackedMainErr;
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wire wMainFlush;
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wire wMainFlushed;
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wire [C_DATA_WIDTH-1:0] wPackedSgRxData;
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wire wPackedSgRxWen;
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wire wPackedSgRxDone;
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wire wPackedSgRxErr;
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wire wSgRxFlush;
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wire wSgRxFlushed;
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wire [C_DATA_WIDTH-1:0] wPackedSgTxData;
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wire wPackedSgTxWen;
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wire wPackedSgTxDone;
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wire wPackedSgTxErr;
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wire wSgTxFlush;
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wire wSgTxFlushed;
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wire wMainDataRen;
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wire wMainDataEmpty;
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wire [C_DATA_WIDTH-1:0] wMainData;
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wire wSgRxRst;
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wire wSgRxDataRen;
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wire wSgRxDataEmpty;
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wire [C_DATA_WIDTH-1:0] wSgRxData;
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wire [C_SG_FIFO_DEPTH_WIDTH-1:0] wSgRxFifoCount;
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wire wSgTxRst;
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wire [C_SG_FIFO_DEPTH_WIDTH-1:0] wSgTxFifoCount;
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wire wSgRxReq;
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wire [63:0] wSgRxReqAddr;
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wire [9:0] wSgRxReqLen;
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wire wSgTxReq;
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wire [63:0] wSgTxReqAddr;
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wire [9:0] wSgTxReqLen;
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wire wSgRxReqProc;
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wire wSgTxReqProc;
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wire wMainReqProc;
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wire wReqAck;
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wire wSgElemRdy;
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wire wSgElemRen;
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wire [63:0] wSgElemAddr;
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wire [31:0] wSgElemLen;
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wire wSgRst;
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wire wMainReq;
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wire [63:0] wMainReqAddr;
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wire [9:0] wMainReqLen;
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wire wTxnErr;
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wire wChnlRx;
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wire wChnlRxRecvd;
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wire wChnlRxAckRecvd;
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wire wChnlRxLast;
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wire [31:0] wChnlRxLen;
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wire [30:0] wChnlRxOff;
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wire [31:0] wChnlRxConsumed;
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reg [4:0] rWideRst=0;
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reg rRst=0;
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assign SG_ERR = (wPackedSgTxDone & wPackedSgTxErr);
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// Generate a wide reset from the input reset.
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always @ (posedge CLK) begin
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rRst <= #1 rWideRst[4];
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if (RST)
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rWideRst <= #1 5'b11111;
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else
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rWideRst <= (rWideRst<<1);
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end
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// Pack received data tightly into our FIFOs
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fifo_packer_128 mainFifoPacker (
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.CLK(CLK),
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.RST(rRst),
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.DATA_IN(MAIN_DATA),
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.DATA_IN_EN(MAIN_DATA_EN),
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.DATA_IN_DONE(MAIN_DONE),
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.DATA_IN_ERR(MAIN_ERR),
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.DATA_IN_FLUSH(wMainFlush),
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.PACKED_DATA(wPackedMainData),
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.PACKED_WEN(wPackedMainWen),
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.PACKED_DATA_DONE(wPackedMainDone),
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.PACKED_DATA_ERR(wPackedMainErr),
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.PACKED_DATA_FLUSHED(wMainFlushed)
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);
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fifo_packer_128 sgRxFifoPacker (
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.CLK(CLK),
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.RST(rRst),
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.DATA_IN(SG_RX_DATA),
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.DATA_IN_EN(SG_RX_DATA_EN),
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.DATA_IN_DONE(SG_RX_DONE),
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.DATA_IN_ERR(SG_RX_ERR),
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.DATA_IN_FLUSH(wSgRxFlush),
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.PACKED_DATA(wPackedSgRxData),
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.PACKED_WEN(wPackedSgRxWen),
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.PACKED_DATA_DONE(wPackedSgRxDone),
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.PACKED_DATA_ERR(wPackedSgRxErr),
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.PACKED_DATA_FLUSHED(wSgRxFlushed)
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);
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fifo_packer_128 sgTxFifoPacker (
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.CLK(CLK),
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.RST(rRst),
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.DATA_IN(SG_TX_DATA),
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.DATA_IN_EN(SG_TX_DATA_EN),
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.DATA_IN_DONE(SG_TX_DONE),
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.DATA_IN_ERR(SG_TX_ERR),
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.DATA_IN_FLUSH(wSgTxFlush),
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.PACKED_DATA(wPackedSgTxData),
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.PACKED_WEN(wPackedSgTxWen),
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.PACKED_DATA_DONE(wPackedSgTxDone),
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.PACKED_DATA_ERR(wPackedSgTxErr),
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.PACKED_DATA_FLUSHED(wSgTxFlushed)
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);
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// FIFOs for storing received data for the channel.
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(* RAM_STYLE="BLOCK" *)
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async_fifo_fwft #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_MAIN_FIFO_DEPTH)) mainFifo (
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.WR_CLK(CLK),
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.WR_RST(rRst | (wTxnErr & TXN_DONE) | wSgRst),
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.WR_EN(wPackedMainWen),
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.WR_DATA(wPackedMainData),
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.WR_FULL(),
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.RD_CLK(CHNL_CLK),
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.RD_RST(rRst | (wTxnErr & TXN_DONE) | wSgRst),
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.RD_EN(wMainDataRen),
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.RD_DATA(wMainData),
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.RD_EMPTY(wMainDataEmpty)
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);
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(* RAM_STYLE="BLOCK" *)
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sync_fifo #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_SG_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) sgRxFifo (
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.RST(rRst | wSgRxRst),
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.CLK(CLK),
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.WR_EN(wPackedSgRxWen),
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.WR_DATA(wPackedSgRxData),
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.FULL(),
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.RD_EN(wSgRxDataRen),
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.RD_DATA(wSgRxData),
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.EMPTY(wSgRxDataEmpty),
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.COUNT(wSgRxFifoCount)
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);
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(* RAM_STYLE="BLOCK" *)
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sync_fifo #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_SG_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) sgTxFifo (
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.RST(rRst | wSgTxRst),
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.CLK(CLK),
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.WR_EN(wPackedSgTxWen),
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.WR_DATA(wPackedSgTxData),
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.FULL(),
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.RD_EN(SG_DATA_REN),
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.RD_DATA(SG_DATA),
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.EMPTY(SG_DATA_EMPTY),
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.COUNT(wSgTxFifoCount)
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);
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// Manage requesting and acknowledging scatter gather data. Note that
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// these modules will share the main requestor's RX channel. They will
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// take priority over the main logic's use of the RX channel.
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sg_list_requester #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_SG_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) sgRxReq (
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.CLK(CLK),
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.RST(rRst),
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.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
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.USER_RST(wSgRst),
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.BUF_RECVD(SG_RX_BUF_RECVD),
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.BUF_DATA(SG_RX_BUF_DATA),
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.BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
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.BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
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.BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
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.FIFO_COUNT(wSgRxFifoCount),
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.FIFO_FLUSH(wSgRxFlush),
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.FIFO_FLUSHED(wSgRxFlushed),
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.FIFO_RST(wSgRxRst),
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.RX_REQ(wSgRxReq),
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.RX_ADDR(wSgRxReqAddr),
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.RX_LEN(wSgRxReqLen),
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.RX_REQ_ACK(wReqAck & wSgRxReqProc),
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.RX_DONE(wPackedSgRxDone)
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);
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sg_list_requester #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_SG_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) sgTxReq (
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.CLK(CLK),
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.RST(rRst),
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.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
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.USER_RST(SG_RST),
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.BUF_RECVD(SG_TX_BUF_RECVD),
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.BUF_DATA(SG_TX_BUF_DATA),
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.BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
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.BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
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.BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
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.FIFO_COUNT(wSgTxFifoCount),
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.FIFO_FLUSH(wSgTxFlush),
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.FIFO_FLUSHED(wSgTxFlushed),
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.FIFO_RST(wSgTxRst),
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.RX_REQ(wSgTxReq),
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.RX_ADDR(wSgTxReqAddr),
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.RX_LEN(wSgTxReqLen),
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.RX_REQ_ACK(wReqAck & wSgTxReqProc),
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.RX_DONE(wPackedSgTxDone)
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);
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// A read requester for the channel and scatter gather requesters.
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rx_port_requester_mux requesterMux (
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.RST(rRst),
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.CLK(CLK),
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.SG_RX_REQ(wSgRxReq),
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.SG_RX_LEN(wSgRxReqLen),
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.SG_RX_ADDR(wSgRxReqAddr),
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.SG_RX_REQ_PROC(wSgRxReqProc),
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.SG_TX_REQ(wSgTxReq),
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.SG_TX_LEN(wSgTxReqLen),
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.SG_TX_ADDR(wSgTxReqAddr),
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.SG_TX_REQ_PROC(wSgTxReqProc),
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.MAIN_REQ(wMainReq),
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.MAIN_LEN(wMainReqLen),
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.MAIN_ADDR(wMainReqAddr),
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.MAIN_REQ_PROC(wMainReqProc),
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.RX_REQ(RX_REQ),
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.RX_REQ_ACK(RX_REQ_ACK),
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.RX_REQ_TAG(RX_REQ_TAG),
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.RX_REQ_ADDR(RX_REQ_ADDR),
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.RX_REQ_LEN(RX_REQ_LEN),
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.REQ_ACK(wReqAck)
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);
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// Read the scatter gather buffer address and length, continuously so that
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// we have it ready whenever the next buffer is needed.
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sg_list_reader_128 #(.C_DATA_WIDTH(C_DATA_WIDTH)) sgListReader (
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.CLK(CLK),
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.RST(rRst | wSgRst),
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.BUF_DATA(wSgRxData),
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.BUF_DATA_EMPTY(wSgRxDataEmpty),
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.BUF_DATA_REN(wSgRxDataRen),
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.VALID(wSgElemRdy),
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.EMPTY(),
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.REN(wSgElemRen),
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.ADDR(wSgElemAddr),
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.LEN(wSgElemLen)
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);
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// Main port reader logic
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rx_port_reader #(.C_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_MAIN_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) reader (
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.CLK(CLK),
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.RST(rRst),
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.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
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.TXN_DATA(TXN_DATA),
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.TXN_LEN_VALID(TXN_LEN_VALID),
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.TXN_OFF_LAST_VALID(TXN_OFF_LAST_VALID),
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.TXN_DONE_LEN(TXN_DONE_LEN),
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.TXN_DONE(TXN_DONE),
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.TXN_ERR(wTxnErr),
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.TXN_DONE_ACK(TXN_DONE_ACK),
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.TXN_DATA_FLUSH(wMainFlush),
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.TXN_DATA_FLUSHED(wMainFlushed),
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.RX_REQ(wMainReq),
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.RX_ADDR(wMainReqAddr),
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.RX_LEN(wMainReqLen),
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.RX_REQ_ACK(wReqAck & wMainReqProc),
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.RX_DATA_EN(MAIN_DATA_EN),
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.RX_DONE(wPackedMainDone),
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.RX_ERR(wPackedMainErr),
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.SG_DONE(wPackedSgRxDone),
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.SG_ERR(wPackedSgRxErr),
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.SG_ELEM_ADDR(wSgElemAddr),
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.SG_ELEM_LEN(wSgElemLen),
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.SG_ELEM_RDY(wSgElemRdy),
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.SG_ELEM_REN(wSgElemRen),
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.SG_RST(wSgRst),
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.CHNL_RX(wChnlRx),
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.CHNL_RX_LEN(wChnlRxLen),
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.CHNL_RX_LAST(wChnlRxLast),
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.CHNL_RX_OFF(wChnlRxOff),
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.CHNL_RX_RECVD(wChnlRxRecvd),
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.CHNL_RX_ACK_RECVD(wChnlRxAckRecvd),
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.CHNL_RX_CONSUMED(wChnlRxConsumed)
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);
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// Manage the CHNL_RX* signals in the CHNL_CLK domain.
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rx_port_channel_gate #(.C_DATA_WIDTH(C_DATA_WIDTH)) gate (
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.RST(rRst),
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|
.CLK(CLK),
|
|
.RX(wChnlRx),
|
|
.RX_RECVD(wChnlRxRecvd),
|
|
.RX_ACK_RECVD(wChnlRxAckRecvd),
|
|
.RX_LAST(wChnlRxLast),
|
|
.RX_LEN(wChnlRxLen),
|
|
.RX_OFF(wChnlRxOff),
|
|
.RX_CONSUMED(wChnlRxConsumed),
|
|
.RD_DATA(wMainData),
|
|
.RD_EMPTY(wMainDataEmpty),
|
|
.RD_EN(wMainDataRen),
|
|
.CHNL_CLK(CHNL_CLK),
|
|
.CHNL_RX(CHNL_RX),
|
|
.CHNL_RX_ACK(CHNL_RX_ACK),
|
|
.CHNL_RX_LAST(CHNL_RX_LAST),
|
|
.CHNL_RX_LEN(CHNL_RX_LEN),
|
|
.CHNL_RX_OFF(CHNL_RX_OFF),
|
|
.CHNL_RX_DATA(CHNL_RX_DATA),
|
|
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID),
|
|
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
|
|
);
|
|
|
|
|
|
|
|
/*
|
|
reg [31:0] rCounter=0;
|
|
always @ (posedge CLK) begin
|
|
if (RST)
|
|
rCounter <= #1 0;
|
|
else
|
|
rCounter <= #1 (RX_REQ_ACK ? rCounter + 1 : rCounter);
|
|
end
|
|
|
|
|
|
wire [35:0] wControl0;
|
|
chipscope_icon_1 cs_icon(
|
|
.CONTROL0(wControl0)
|
|
);
|
|
|
|
chipscope_ila_t8_512_max a0(
|
|
.CLK(CLK),
|
|
.CONTROL(wControl0),
|
|
.TRIG0({(SG_RX_DATA_EN != 0) | (MAIN_DATA_EN != 0),
|
|
RX_REQ_ACK,
|
|
wSgElemRen,
|
|
(SG_RX_BUF_ADDR_LO_VALID | SG_RX_BUF_ADDR_HI_VALID | SG_RX_BUF_LEN_VALID | SG_TX_BUF_ADDR_HI_VALID | SG_TX_BUF_LEN_VALID | TXN_OFF_LAST_VALID | TXN_LEN_VALID | wSgRst),
|
|
rCounter[10:7]}),
|
|
// .TRIG0({wSgRxReq & wSgRxReqProc & wReqAck,
|
|
// wSgElemRen,
|
|
// wMainReq | wSgRxReq | wSgTxReq,
|
|
// (SG_RX_DATA_EN != 0),
|
|
// SG_RX_BUF_ADDR_LO_VALID | SG_RX_BUF_ADDR_HI_VALID | SG_RX_BUF_LEN_VALID | TXN_OFF_LAST_VALID | TXN_LEN_VALID,
|
|
// rSgElemRenCount > 1100,
|
|
// wSgRst | wTxnErr | wSgRxFlush | wSgRxFlushed,
|
|
// wPackedSgRxDone | wPackedSgRxErr}),
|
|
.DATA({
|
|
MAIN_DATA_EN, // 3
|
|
//wPackedSgRxData, // 128
|
|
SG_RX_DONE, // 1
|
|
SG_RX_DATA_EN, // 3
|
|
SG_RX_DATA, // 128
|
|
wSgRxDataRen, // 1
|
|
wSgRxDataEmpty, // 1
|
|
MAIN_DATA, // 128
|
|
wSgRst, // 1
|
|
SG_RST, // 1
|
|
wPackedSgRxDone, // 1
|
|
wSgRxRst, // 1
|
|
wSgRxFlushed, // 1
|
|
wSgRxFlush, // 1
|
|
SG_RX_BUF_ADDR_LO_VALID, // 1
|
|
SG_RX_BUF_ADDR_HI_VALID, // 1
|
|
SG_RX_BUF_LEN_VALID, // 1
|
|
//SG_RX_BUF_DATA, // 32
|
|
rCounter, // 32
|
|
RX_REQ_ADDR, // 64
|
|
RX_REQ_TAG, // 2
|
|
RX_REQ_ACK, // 1
|
|
RX_REQ, // 1
|
|
wSgTxReqProc, // 1
|
|
wSgTxReq, // 1
|
|
wSgRxReqProc, // 1
|
|
//wSgRxReqAddr, // 64
|
|
//wSgElemAddr, // 64
|
|
44'd0, // 44
|
|
wSgRxReqLen, // 10
|
|
RX_REQ_LEN, // 10
|
|
wSgRxReq, // 1
|
|
wMainReqProc, // 1
|
|
wMainReqAddr, // 64
|
|
wMainReq, // 1
|
|
wReqAck, // 1
|
|
wTxnErr, // 1
|
|
TXN_OFF_LAST_VALID, // 1
|
|
TXN_LEN_VALID}) // 1
|
|
);
|
|
*/
|
|
|
|
endmodule
|