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FPGA
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riffa
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riffa
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fpga
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Dustin Richmond
753ffffd93
Fixed a bug where a clock ratio of less than 1:2 between the user-provided clock
...
and the PCIe core clock would cause some transfers to return 0 words (but not hang).
2016-02-16 16:02:42 -08:00
..
altera
Updating copyright statements for 2016
2016-02-09 15:23:37 -08:00
riffa_hdl
Fixed a bug where a clock ratio of less than 1:2 between the user-provided clock
2016-02-16 16:02:42 -08:00
xilinx
Updating copyright statements for 2016
2016-02-09 15:23:37 -08:00
Makefile
Updating copyright statements for 2016
2016-02-09 15:23:37 -08:00