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riffa/fpga/riffa_hdl/functions.vh

36 lines
618 B
Systemverilog

`ifndef __FUNCTIONS_VH
`define __FUNCTIONS_VH 1
function integer clog2;
input [31:0] v;
reg [31:0] value;
begin
value = v;
if (value == 1) begin
clog2 = 0;
end
else begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
end
endfunction
// clog2s -- calculate the ceiling log2 value, min return is 1 (safe).
function integer clog2s;
input [31:0] v;
reg [31:0] value;
begin
value = v;
if (value == 1) begin
clog2s = 1;
end
else begin
value = value-1;
for (clog2s=0; value>0; clog2s=clog2s+1)
value = value>>1;
end
end
endfunction
`endif