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981 lines
45 KiB
Verilog
981 lines
45 KiB
Verilog
// ----------------------------------------------------------------------
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// Copyright (c) 2015, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Filename: rxr_engine_classic.v
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// Version: 1.0
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// Verilog Standard: Verilog-2001
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// Description: The RXR Engine (Classic) takes a single stream of TLP
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// packets and provides the request packets on the RXR Interface.
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// This Engine is capable of operating at "line rate".
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// Author: Dustin Richmond (@darichmond)
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//-----------------------------------------------------------------------------
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`timescale 1ns/1ns
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`include "trellis.vh"
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`include "tlp.vh"
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module rxr_engine_classic
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#(parameter C_VENDOR = "ALTERA",
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parameter C_PCI_DATA_WIDTH = 128,
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parameter C_RX_PIPELINE_DEPTH=10
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)
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(
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// Interface: Clocks
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input CLK,
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// Interface: Resets
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input RST_IN,
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// Interface: RX Classic
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input [C_PCI_DATA_WIDTH-1:0] RX_TLP,
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input RX_TLP_VALID,
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input RX_TLP_START_FLAG,
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input [`SIG_OFFSET_W-1:0] RX_TLP_START_OFFSET,
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input RX_TLP_END_FLAG,
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input [`SIG_OFFSET_W-1:0] RX_TLP_END_OFFSET,
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input [`SIG_BARDECODE_W-1:0] RX_TLP_BAR_DECODE,
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// Interface: RXR
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output [C_PCI_DATA_WIDTH-1:0] RXR_DATA,
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output RXR_DATA_VALID,
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output [(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_WORD_ENABLE,
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output RXR_DATA_START_FLAG,
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output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET,
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output RXR_DATA_END_FLAG,
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output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET,
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output [`SIG_FBE_W-1:0] RXR_META_FDWBE,
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output [`SIG_LBE_W-1:0] RXR_META_LDWBE,
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output [`SIG_TC_W-1:0] RXR_META_TC,
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output [`SIG_ATTR_W-1:0] RXR_META_ATTR,
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output [`SIG_TAG_W-1:0] RXR_META_TAG,
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output [`SIG_TYPE_W-1:0] RXR_META_TYPE,
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output [`SIG_ADDR_W-1:0] RXR_META_ADDR,
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output [`SIG_BARDECODE_W-1:0] RXR_META_BAR_DECODED,
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output [`SIG_REQID_W-1:0] RXR_META_REQUESTER_ID,
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output [`SIG_LEN_W-1:0] RXR_META_LENGTH,
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output RXR_META_EP,
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// Interface: RX Shift Register
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input [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] RX_SR_DATA,
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input [C_RX_PIPELINE_DEPTH:0] RX_SR_EOP,
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input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0] RX_SR_END_OFFSET,
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input [C_RX_PIPELINE_DEPTH:0] RX_SR_SOP,
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input [C_RX_PIPELINE_DEPTH:0] RX_SR_VALID
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);
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/*AUTOWIRE*/
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///*AUTOOUTPUT*/
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// End of automatics
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localparam C_RX_BE_W = (`SIG_FBE_W+`SIG_LBE_W);
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localparam C_RX_INPUT_STAGES = 1;
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localparam C_RX_OUTPUT_STAGES = 1; // Must always be at least one
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localparam C_RX_COMPUTATION_STAGES = 1;
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localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES;
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// Cycle index in the SOP register when enable is raised
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// Computation can begin when the last DW of the header is recieved.
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localparam C_RX_COMPUTATION_CYCLE = C_RX_COMPUTATION_STAGES + (`TLP_REQADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
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// The computation cycle must be at least one cycle before the address is enabled
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localparam C_RX_DATA_CYCLE = C_RX_COMPUTATION_CYCLE;
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localparam C_RX_ADDRDW0_CYCLE = (`TLP_REQADDRDW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
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localparam C_RX_ADDRDW1_CYCLE = (`TLP_REQADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
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localparam C_RX_METADW0_CYCLE = (`TLP_REQMETADW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
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localparam C_RX_METADW1_CYCLE = (`TLP_REQMETADW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
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localparam C_RX_ADDRDW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQADDRDW0_I%C_PCI_DATA_WIDTH);
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localparam C_RX_ADDRDW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQADDRDW1_I%C_PCI_DATA_WIDTH);
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localparam C_RX_ADDRDW1_RESET_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES +
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C_PCI_DATA_WIDTH*(C_RX_ADDRDW1_CYCLE - C_RX_METADW0_CYCLE) +
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`TLP_4DWHBIT_I;
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localparam C_RX_METADW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQMETADW0_I%C_PCI_DATA_WIDTH);
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localparam C_RX_METADW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQMETADW1_I%C_PCI_DATA_WIDTH);
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localparam C_OFFSET_WIDTH = clog2s(C_PCI_DATA_WIDTH/32);
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localparam C_MAX_ABLANK_WIDTH = 32;
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localparam C_MAX_START_OFFSET = (`TLP_MAXHDR_W + C_MAX_ABLANK_WIDTH)/32;
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localparam C_STD_START_DELAY = (64/C_PCI_DATA_WIDTH);
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wire [63:0] wAddrFmt;
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wire [63:0] wMetadata;
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wire [`TLP_TYPE_W-1:0] wType;
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wire [`TLP_LEN_W-1:0] wLength;
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wire wAddrDW0Bit2;
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wire wAddrDW1Bit2;
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wire wAddrHiReset;
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wire [31:0] wAddrMux[(`TLP_REQADDR_W / 32)-1:0];
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wire [63:0] wAddr;
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wire w4DWH;
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wire wHasPayload;
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wire [2:0] wHdrLength;
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wire [2:0] wHdrLengthM1;
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wire [(C_PCI_DATA_WIDTH/32)-1:0] wEndMask;
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wire _wEndFlag;
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wire wEndFlag;
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wire [C_OFFSET_WIDTH-1:0] wEndOffset;
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wire [(C_PCI_DATA_WIDTH/32)-1:0] wStartMask;
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wire [3:0] wStartFlags;
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wire wStartFlag;
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wire _wStartFlag;
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wire [clog2s(C_MAX_START_OFFSET)-1:0] wStartOffset;
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wire wInsertBlank;
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wire wRotateAddressField;
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wire [C_PCI_DATA_WIDTH-1:0] wRxrData;
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wire [`SIG_ADDR_W-1:0] wRxrMetaAddr;
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wire [63:0] wRxrMetadata;
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wire wRxrDataValid;
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wire wRxrDataReady; // Pinned High
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wire wRxrDataEndFlag;
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wire [C_OFFSET_WIDTH-1:0] wRxrDataEndOffset;
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wire [(C_PCI_DATA_WIDTH/32)-1:0] wRxrDataWordEnable;
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wire wRxrDataStartFlag;
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wire [C_OFFSET_WIDTH-1:0] wRxrDataStartOffset;
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wire [C_RX_PIPELINE_DEPTH:0] wRxSrSop;
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reg rValid,_rValid;
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assign wAddrHiReset = ~RX_SR_DATA[C_RX_ADDRDW1_RESET_INDEX];
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// Select Addr[31:0] from one of the two possible locations in the TLP based
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// on header length (1 bit)
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assign wRotateAddressField = w4DWH;
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assign wAddrFmt = {wAddrMux[~wRotateAddressField],wAddrMux[wRotateAddressField]};
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assign wAddrMux[0] = wAddr[31:0];
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assign wAddrMux[1] = wAddr[63:32];
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// Calculate the header length (start offset), and header length minus 1 (end offset)
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assign wHdrLength = {w4DWH,~w4DWH,~w4DWH};
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assign wHdrLengthM1 = {1'b0,1'b1,w4DWH};
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// Determine if the TLP has an inserted blank before the payload
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assign wInsertBlank = ((w4DWH & wAddrDW1Bit2) | (~w4DWH & ~wAddrDW0Bit2)) & (C_VENDOR == "ALTERA");
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assign wStartOffset = (wHdrLength + {2'd0,wInsertBlank}); // Start offset in dwords
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assign wEndOffset = wHdrLengthM1 + wInsertBlank + wLength;//RX_SR_END_OFFSET[(C_TOTAL_STAGES-1)*`SIG_OFFSET_W +: C_OFFSET_WIDTH];
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// Inputs
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// Technically an input, but the trellis protocol specifies it must be held high at all times
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assign wRxrDataReady = 1;
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// Outputs
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assign RXR_DATA = RX_SR_DATA[(C_TOTAL_STAGES)*C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];
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assign RXR_DATA_VALID = wRxrDataValid;
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assign RXR_DATA_END_FLAG = wRxrDataEndFlag;
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assign RXR_DATA_END_OFFSET = wRxrDataEndOffset;
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assign RXR_DATA_START_FLAG = wRxrDataStartFlag;
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assign RXR_DATA_START_OFFSET = wRxrDataStartOffset;
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assign RXR_META_BAR_DECODED = 0;
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assign RXR_META_LENGTH = wRxrMetadata[`TLP_LEN_R];
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assign RXR_META_TC = wRxrMetadata[`TLP_TC_R];
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assign RXR_META_ATTR = {wRxrMetadata[`TLP_ATTR1_R], wRxrMetadata[`TLP_ATTR0_R]};
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assign RXR_META_TYPE = tlp_to_trellis_type({wRxrMetadata[`TLP_FMT_R],wRxrMetadata[`TLP_TYPE_R]});
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assign RXR_META_ADDR = wRxrMetaAddr;
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assign RXR_META_REQUESTER_ID = wRxrMetadata[`TLP_REQREQID_R];
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assign RXR_META_TAG = wRxrMetadata[`TLP_REQTAG_R];
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assign RXR_META_FDWBE = wRxrMetadata[`TLP_REQFBE_R];
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assign RXR_META_LDWBE = wRxrMetadata[`TLP_REQLBE_R];
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assign RXR_META_EP = wRxrMetadata[`TLP_EP_R];
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assign _wEndFlag = RX_SR_EOP[C_RX_INPUT_STAGES];
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assign wEndFlag = RX_SR_EOP[C_RX_INPUT_STAGES+1];
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assign _wStartFlag = wStartFlags != 0;
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generate
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if(C_PCI_DATA_WIDTH == 32) begin
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assign wStartFlags[3] = 0;
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assign wStartFlags[2] = wRxSrSop[C_RX_INPUT_STAGES + 3] & wMetadata[`TLP_PAYBIT_I] & ~rValid; // Any remaining cases
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assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 2] & wMetadata[`TLP_PAYBIT_I] & ~wMetadata[`TLP_4DWHBIT_I]; // 3DWH, No Blank
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assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES + 2] & ~wMetadata[`TLP_PAYBIT_I]; // No Payload
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end else if(C_PCI_DATA_WIDTH == 64) begin
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assign wStartFlags[3] = 0;
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assign wStartFlags[2] = wRxSrSop[C_RX_INPUT_STAGES + 2] & wMetadata[`TLP_PAYBIT_I] & ~rValid; // Any remaining cases
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if(C_VENDOR == "ALTERA") begin
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assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wMetadata[`TLP_PAYBIT_I] & ~wMetadata[`TLP_4DWHBIT_I] & RX_SR_DATA[C_RX_ADDRDW0_INDEX + 2]; // 3DWH, No Blank
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end else begin
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assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wMetadata[`TLP_PAYBIT_I] & ~wMetadata[`TLP_4DWHBIT_I]; // 3DWH, No Blank
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end
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assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES + 1] & ~wMetadata[`TLP_PAYBIT_I]; // No Payload
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end else if (C_PCI_DATA_WIDTH == 128) begin
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assign wStartFlags[3] = 0;
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assign wStartFlags[2] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wMetadata[`TLP_PAYBIT_I] & ~rValid; // Is this correct?
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if(C_VENDOR == "ALTERA") begin
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assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES] & RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_PAYBIT_I] & ~RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_4DWHBIT_I] & RX_SR_DATA[C_RX_ADDRDW0_INDEX + 2]; // 3DWH, No Blank
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end else begin
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assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES] & RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_PAYBIT_I] & ~RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_4DWHBIT_I];
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end
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assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES] & ~RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_PAYBIT_I]; // No Payload
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end else begin // 256
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assign wStartFlags[3] = 0;
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assign wStartFlags[2] = 0;
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assign wStartFlags[1] = 0;
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assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES];
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end // else: !if(C_PCI_DATA_WIDTH == 128)
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endgenerate
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always @(*) begin
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_rValid = rValid;
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if(_wStartFlag) begin
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_rValid = 1'b1;
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end else if (wEndFlag) begin
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_rValid = 1'b0;
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end
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end
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always @(posedge CLK) begin
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if(RST_IN) begin
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rValid <= 1'b0;
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end else begin
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rValid <= _rValid;
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end
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end
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assign wStartMask = {C_PCI_DATA_WIDTH/32{1'b1}} << ({C_OFFSET_WIDTH{wStartFlag}}& wStartOffset[C_OFFSET_WIDTH-1:0]);
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offset_to_mask
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#(// Parameters
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.C_MASK_SWAP (0),
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.C_MASK_WIDTH (C_PCI_DATA_WIDTH/32)
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/*AUTOINSTPARAM*/)
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o2m_ef
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(
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// Outputs
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.MASK (wEndMask),
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// Inputs
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.OFFSET_ENABLE (wEndFlag),
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.OFFSET (wEndOffset[C_OFFSET_WIDTH-1:0])
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/*AUTOINST*/);
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generate
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if(C_RX_OUTPUT_STAGES == 0) begin
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assign RXR_DATA_WORD_ENABLE = {wEndMask & wStartMask} & {C_PCI_DATA_WIDTH/32{~rValid | ~wMetadata[`TLP_PAYBIT_I]}};
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end else begin
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register
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#(
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// Parameters
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.C_WIDTH (C_PCI_DATA_WIDTH/32),
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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dw_enable
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(// Outputs
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.RD_DATA (wRxrDataWordEnable),
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// Inputs
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.RST_IN (~rValid | ~wMetadata[`TLP_PAYBIT_I]),
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.WR_DATA (wEndMask & wStartMask),
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.WR_EN (1),
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/*AUTOINST*/
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.CLK (CLK));
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pipeline
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#(
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// Parameters
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.C_DEPTH (C_RX_OUTPUT_STAGES-1),
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.C_WIDTH (C_PCI_DATA_WIDTH/32),
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.C_USE_MEMORY (0)
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/*AUTOINSTPARAM*/)
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dw_pipeline
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(
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// Outputs
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.WR_DATA_READY (), // Pinned to 1
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.RD_DATA (RXR_DATA_WORD_ENABLE),
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.RD_DATA_VALID (),
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// Inputs
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.WR_DATA (wRxrDataWordEnable),
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.WR_DATA_VALID (1),
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.RD_DATA_READY (1'b1),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN));
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end
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endgenerate
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register
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#(
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// Parameters
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.C_WIDTH (32),
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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metadata_DW0_register
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(
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// Outputs
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.RD_DATA (wMetadata[31:0]),
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// Inputs
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.WR_DATA (RX_SR_DATA[C_RX_METADW0_INDEX +: 32]),
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.WR_EN (wRxSrSop[C_RX_METADW0_CYCLE]),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN));
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register
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#(
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// Parameters
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.C_WIDTH (32),
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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meta_DW1_register
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(
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// Outputs
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.RD_DATA (wMetadata[63:32]),
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// Inputs
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.WR_DATA (RX_SR_DATA[C_RX_METADW1_INDEX +: 32]),
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.WR_EN (wRxSrSop[C_RX_METADW1_CYCLE]),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN));
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register
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#(
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// Parameters
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.C_WIDTH (32),
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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addr_DW0_register
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(
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// Outputs
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.RD_DATA (wAddr[31:0]),
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// Inputs
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.WR_DATA (RX_SR_DATA[C_RX_ADDRDW0_INDEX +: 32]),
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.WR_EN (wRxSrSop[C_RX_ADDRDW0_CYCLE]),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN));
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register
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#(
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// Parameters
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.C_WIDTH (32),
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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addr_DW1_register
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(
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// Outputs
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.RD_DATA (wAddr[63:32]),
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// Inputs
|
|
.WR_DATA (RX_SR_DATA[C_RX_ADDRDW1_INDEX +: 32]),
|
|
.WR_EN (wRxSrSop[C_RX_ADDRDW1_CYCLE]),
|
|
.RST_IN (RST_IN | (wAddrHiReset & wRxSrSop[C_RX_ADDRDW1_CYCLE])),
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.CLK (CLK));
|
|
|
|
register
|
|
#(
|
|
// Parameters
|
|
.C_WIDTH (2),
|
|
.C_VALUE (0)
|
|
/*AUTOINSTPARAM*/)
|
|
metadata_4DWH_register
|
|
(
|
|
// Outputs
|
|
.RD_DATA ({wHasPayload,w4DWH}),
|
|
// Inputs
|
|
.WR_DATA (RX_SR_DATA[`TLP_FMT_I + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES +: 2]),
|
|
.WR_EN (wRxSrSop[`TLP_4DWHBIT_I/C_PCI_DATA_WIDTH + C_RX_INPUT_STAGES]),
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.CLK (CLK),
|
|
.RST_IN (RST_IN));
|
|
|
|
register
|
|
#(
|
|
// Parameters
|
|
.C_WIDTH (`TLP_TYPE_W),
|
|
.C_VALUE (0)
|
|
/*AUTOINSTPARAM*/)
|
|
metadata_type_register
|
|
(
|
|
// Outputs
|
|
.RD_DATA (wType),
|
|
// Inputs
|
|
.WR_DATA (RX_SR_DATA[(`TLP_TYPE_I/* + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES*/) +: `TLP_TYPE_W]),
|
|
.WR_EN (wRxSrSop[`TLP_TYPE_I/C_PCI_DATA_WIDTH/* + C_RX_INPUT_STAGES*/]),
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.CLK (CLK),
|
|
.RST_IN (RST_IN));
|
|
|
|
register
|
|
#(
|
|
// Parameters
|
|
.C_WIDTH (`TLP_LEN_W),
|
|
.C_VALUE (0)
|
|
/*AUTOINSTPARAM*/)
|
|
metadata_length_register
|
|
(
|
|
// Outputs
|
|
.RD_DATA (wLength),
|
|
// Inputs
|
|
.WR_DATA (RX_SR_DATA[(`TLP_LEN_I + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES) +: `TLP_LEN_W]),
|
|
.WR_EN (wRxSrSop[`TLP_LEN_I/C_PCI_DATA_WIDTH + C_RX_INPUT_STAGES]),
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.CLK (CLK),
|
|
.RST_IN (RST_IN));
|
|
|
|
|
|
register
|
|
#(
|
|
// Parameters
|
|
.C_WIDTH (1),
|
|
.C_VALUE (0)
|
|
/*AUTOINSTPARAM*/)
|
|
addr_DW0_bit_2_register
|
|
(
|
|
// Outputs
|
|
.RD_DATA (wAddrDW0Bit2),
|
|
// Inputs
|
|
.CLK (CLK),
|
|
.RST_IN (RST_IN),
|
|
.WR_DATA (RX_SR_DATA[(`TLP_REQADDRDW0_I%C_PCI_DATA_WIDTH) + 2 + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES]),
|
|
.WR_EN (wRxSrSop[(`TLP_REQADDRDW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES]));
|
|
|
|
register
|
|
#(
|
|
// Parameters
|
|
.C_WIDTH (1),
|
|
.C_VALUE (0)
|
|
/*AUTOINSTPARAM*/)
|
|
addr_DW1_bit_2_register
|
|
(
|
|
// Outputs
|
|
.RD_DATA (wAddrDW1Bit2),
|
|
// Inputs
|
|
.WR_DATA (RX_SR_DATA[(`TLP_REQADDRDW1_I%C_PCI_DATA_WIDTH) + 2 + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES]),
|
|
.WR_EN (wRxSrSop[(`TLP_REQADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES]),
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.CLK (CLK),
|
|
.RST_IN (RST_IN));
|
|
|
|
register
|
|
#(
|
|
// Parameters
|
|
.C_WIDTH (1),
|
|
.C_VALUE (0)
|
|
/*AUTOINSTPARAM*/)
|
|
start_flag_register
|
|
(
|
|
// Outputs
|
|
.RD_DATA (wStartFlag),
|
|
// Inputs
|
|
.WR_DATA (_wStartFlag),
|
|
.WR_EN (1),
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.CLK (CLK),
|
|
.RST_IN (RST_IN));
|
|
|
|
pipeline
|
|
#(
|
|
// Parameters
|
|
.C_DEPTH (C_RX_OUTPUT_STAGES),
|
|
.C_WIDTH (`TLP_MAXHDR_W + 2*(1 + C_OFFSET_WIDTH)),
|
|
.C_USE_MEMORY (0)
|
|
/*AUTOINSTPARAM*/)
|
|
output_pipeline
|
|
(
|
|
// Outputs
|
|
.WR_DATA_READY (), // Pinned to 1
|
|
.RD_DATA ({wRxrMetadata,wRxrMetaAddr,wRxrDataStartFlag,wRxrDataStartOffset,wRxrDataEndFlag,wRxrDataEndOffset}),
|
|
.RD_DATA_VALID (wRxrDataValid),
|
|
// Inputs
|
|
.WR_DATA ({wMetadata, wAddrFmt, wStartFlag,wStartOffset[C_OFFSET_WIDTH-1:0],wEndFlag,wEndOffset[C_OFFSET_WIDTH-1:0]}),
|
|
.WR_DATA_VALID (rValid),
|
|
.RD_DATA_READY (1'b1),
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.CLK (CLK),
|
|
.RST_IN (RST_IN));
|
|
|
|
// Start Flag Shift Register. Data enables are derived from the
|
|
// taps on this shift register.
|
|
shiftreg
|
|
#(
|
|
// Parameters
|
|
.C_DEPTH (C_RX_PIPELINE_DEPTH),
|
|
.C_WIDTH (1'b1)
|
|
/*AUTOINSTPARAM*/)
|
|
sop_shiftreg_inst
|
|
(
|
|
// Outputs
|
|
.RD_DATA (wRxSrSop),
|
|
// Inputs
|
|
.WR_DATA (RX_TLP_START_FLAG & RX_TLP_VALID & (RX_SR_DATA[`TLP_TYPE_R] == `TLP_TYPE_REQ)),
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.CLK (CLK),
|
|
.RST_IN (RST_IN));
|
|
|
|
endmodule
|
|
module rxr_engine_128
|
|
#(parameter C_PCI_DATA_WIDTH = 128,
|
|
parameter C_RX_PIPELINE_DEPTH=10
|
|
)
|
|
(
|
|
// Interface: Clocks
|
|
input CLK,
|
|
|
|
// Interface: Resets
|
|
input RST_IN,
|
|
|
|
// Interface: RX Classic
|
|
input [C_PCI_DATA_WIDTH-1:0] RX_TLP,
|
|
input RX_TLP_VALID,
|
|
input RX_TLP_START_FLAG,
|
|
input [`SIG_OFFSET_W-1:0] RX_TLP_START_OFFSET,
|
|
input RX_TLP_END_FLAG,
|
|
input [`SIG_OFFSET_W-1:0] RX_TLP_END_OFFSET,
|
|
input [`SIG_BARDECODE_W-1:0] RX_TLP_BAR_DECODE,
|
|
|
|
// Interface: RXR
|
|
output [C_PCI_DATA_WIDTH-1:0] RXR_DATA,
|
|
output RXR_DATA_VALID,
|
|
output [(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_WORD_ENABLE,
|
|
output RXR_DATA_START_FLAG,
|
|
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET,
|
|
output RXR_DATA_END_FLAG,
|
|
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET,
|
|
|
|
output [`SIG_FBE_W-1:0] RXR_META_FDWBE,
|
|
output [`SIG_LBE_W-1:0] RXR_META_LDWBE,
|
|
output [`SIG_TC_W-1:0] RXR_META_TC,
|
|
output [`SIG_ATTR_W-1:0] RXR_META_ATTR,
|
|
output [`SIG_TAG_W-1:0] RXR_META_TAG,
|
|
output [`SIG_TYPE_W-1:0] RXR_META_TYPE,
|
|
output [`SIG_ADDR_W-1:0] RXR_META_ADDR,
|
|
output [`SIG_BARDECODE_W-1:0] RXR_META_BAR_DECODED,
|
|
output [`SIG_REQID_W-1:0] RXR_META_REQUESTER_ID,
|
|
output [`SIG_LEN_W-1:0] RXR_META_LENGTH,
|
|
output RXR_META_EP,
|
|
|
|
// Interface: RX Shift Register
|
|
input [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] RX_SR_DATA,
|
|
input [C_RX_PIPELINE_DEPTH:0] RX_SR_EOP,
|
|
input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0] RX_SR_END_OFFSET,
|
|
input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0] RX_SR_START_OFFSET,
|
|
input [C_RX_PIPELINE_DEPTH:0] RX_SR_SOP,
|
|
input [C_RX_PIPELINE_DEPTH:0] RX_SR_VALID
|
|
);
|
|
|
|
/*AUTOWIRE*/
|
|
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
|
// End of automatics
|
|
///*AUTOOUTPUT*/
|
|
// End of automatics
|
|
localparam C_RX_BE_W = (`SIG_FBE_W+`SIG_LBE_W);
|
|
|
|
localparam C_RX_INPUT_STAGES = 1;
|
|
localparam C_RX_OUTPUT_STAGES = 1;
|
|
localparam C_RX_COMPUTATION_STAGES = 1;
|
|
localparam C_RX_HDR_STAGES = 1; // Specific to the Xilinx 128-bit RXR Engine
|
|
localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES + C_RX_HDR_STAGES;
|
|
|
|
localparam C_OFFSET_WIDTH = clog2s(C_PCI_DATA_WIDTH/32);
|
|
localparam C_STRADDLE_W = 64;
|
|
localparam C_HDR_NOSTRADDLE_I = C_RX_INPUT_STAGES * C_PCI_DATA_WIDTH;
|
|
localparam C_OUTPUT_STAGE_WIDTH = (C_PCI_DATA_WIDTH/32) + 2 + clog2s(C_PCI_DATA_WIDTH/32) + 1 + `SIG_FBE_W + `SIG_LBE_W + `SIG_TC_W + `SIG_ATTR_W + `SIG_TAG_W + `SIG_TYPE_W + `SIG_ADDR_W + `SIG_BARDECODE_W + `SIG_REQID_W + `SIG_LEN_W;
|
|
|
|
// Header Reg Inputs
|
|
wire [`SIG_OFFSET_W-1:0] __wRxrStartOffset;
|
|
wire [`SIG_OFFSET_W-1:0] __wRxrStraddledStartOffset;
|
|
wire [`TLP_MAXHDR_W-1:0] __wRxrHdr;
|
|
wire [`TLP_MAXHDR_W-1:0] __wRxrHdrStraddled;
|
|
wire [`TLP_MAXHDR_W-1:0] __wRxrHdrNotStraddled;
|
|
wire __wRxrHdrValid;
|
|
wire [`TLP_TYPE_W-1:0] __wRxrHdrType;
|
|
wire [`TLP_TYPE_W-1:0] __wRxrHdrTypeStraddled;
|
|
|
|
wire __wRxrHdrSOP; // Asserted on non-straddle SOP
|
|
wire __wRxrHdrSOPStraddle;
|
|
wire __wRxrHdr4DWHWDataSF;
|
|
|
|
// Header Reg Outputs
|
|
wire _wRxrHdrValid;
|
|
wire [`TLP_MAXHDR_W-1:0] _wRxrHdr;
|
|
wire [`SIG_ADDR_W-1:0] _wRxrAddrUnformatted;
|
|
wire [`SIG_ADDR_W-1:0] _wRxrAddr;
|
|
wire [63:0] _wRxrTlpMetadata;
|
|
wire [`TLP_TYPE_W-1:0] _wRxrType;
|
|
wire [`TLP_LEN_W-1:0] _wRxrLength;
|
|
wire [2:0] _wRxrHdrHdrLen;// TODO:
|
|
wire [`SIG_OFFSET_W-1:0] _wRxrHdrStartOffset;// TODO:
|
|
|
|
wire _wRxrHdrDelayedSOP;
|
|
wire _wRxrHdrSOPStraddle;
|
|
wire _wRxrHdrSOP;
|
|
|
|
wire _wRxrHdrSF;
|
|
wire _wRxrHdrEF;
|
|
wire _wRxrHdrSCP; // Single Cycle Packet
|
|
wire _wRxrHdrMCP; // Multi Cycle Packet
|
|
wire _wRxrHdrRegSF;
|
|
wire _wRxrHdrRegValid;
|
|
wire _wRxrHdr4DWHSF;
|
|
wire _wRxrHdr4DWHNoDataSF;
|
|
wire _wRxrHdr4DWHWDataSF;
|
|
wire _wRxrHdr3DWHSF;
|
|
wire [2:0] _wRxrHdrDataSoff;
|
|
wire [1:0] _wRxrHdrDataEoff;
|
|
wire [3:0] _wRxrHdrStartMask;
|
|
wire [3:0] _wRxrHdrEndMask;
|
|
|
|
// Header Reg Outputs
|
|
wire wRxrHdrSF;
|
|
wire wRxrHdrEF;
|
|
wire wRxrHdrValid;
|
|
wire [`TLP_MAXHDR_W-1:0] wRxrHdr;
|
|
wire [63:0] wRxrMetadata;
|
|
wire [`TLP_TYPE_W-1:0] wRxrType;
|
|
wire [`TLP_LEN_W-1:0] wRxrLength;
|
|
wire [2:0] wRxrHdrLength; // TODO:
|
|
wire [`SIG_OFFSET_W-1:0] wRxrHdrStartOffset; // TODO:
|
|
wire wRxrHdrSCP; // Single Cycle Packet
|
|
wire wRxrHdrMCP; // Multi Cycle Packet
|
|
wire [1:0] wRxrHdrDataSoff;
|
|
wire [3:0] wRxrHdrStartMask;
|
|
wire [3:0] wRxrHdrEndMask;
|
|
|
|
// Output Register Inputs
|
|
wire [C_PCI_DATA_WIDTH-1:0] wRxrData;
|
|
wire wRxrDataValid;
|
|
wire [(C_PCI_DATA_WIDTH/32)-1:0] wRxrDataWordEnable;
|
|
wire wRxrDataStartFlag;
|
|
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wRxrDataStartOffset;
|
|
wire wRxrDataEndFlag;
|
|
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wRxrDataEndOffset;
|
|
wire [`SIG_FBE_W-1:0] wRxrMetaFdwbe;
|
|
wire [`SIG_LBE_W-1:0] wRxrMetaLdwbe;
|
|
wire [`SIG_TC_W-1:0] wRxrMetaTC;
|
|
wire [`SIG_ATTR_W-1:0] wRxrMetaAttr;
|
|
wire [`SIG_TAG_W-1:0] wRxrMetaTag;
|
|
wire [`SIG_TYPE_W-1:0] wRxrMetaType;
|
|
wire [`SIG_ADDR_W-1:0] wRxrMetaAddr;
|
|
wire [`SIG_BARDECODE_W-1:0] wRxrMetaBarDecoded;
|
|
wire [`SIG_REQID_W-1:0] wRxrMetaRequesterId;
|
|
wire [`SIG_LEN_W-1:0] wRxrMetaLength;
|
|
wire wRxrMetaEP;
|
|
|
|
reg rStraddledSOP;
|
|
reg rStraddledSOPSplit;
|
|
|
|
// ----- Header Register -----
|
|
assign __wRxrHdrSOP = RX_SR_SOP[C_RX_INPUT_STAGES] & ~__wRxrStartOffset[1];
|
|
assign __wRxrHdrSOPStraddle = RX_SR_SOP[C_RX_INPUT_STAGES] & __wRxrStraddledStartOffset[1];
|
|
|
|
assign __wRxrHdrNotStraddled = RX_SR_DATA[C_HDR_NOSTRADDLE_I +: C_PCI_DATA_WIDTH];
|
|
assign __wRxrHdrStraddled = {RX_SR_DATA[C_RX_INPUT_STAGES*C_PCI_DATA_WIDTH +: C_STRADDLE_W],
|
|
RX_SR_DATA[(C_RX_INPUT_STAGES+1)*C_PCI_DATA_WIDTH + C_STRADDLE_W +: C_STRADDLE_W ]};
|
|
assign __wRxrStartOffset = RX_SR_START_OFFSET[`SIG_OFFSET_W*C_RX_INPUT_STAGES +: `SIG_OFFSET_W];
|
|
assign __wRxrStraddledStartOffset = RX_SR_START_OFFSET[`SIG_OFFSET_W*(C_RX_INPUT_STAGES) +: `SIG_OFFSET_W];
|
|
assign __wRxrHdrValid = __wRxrHdrSOP | ((rStraddledSOP | rStraddledSOPSplit) & RX_SR_VALID[C_RX_INPUT_STAGES]);
|
|
assign __wRxrHdr4DWHWDataSF = (_wRxrHdr[`TLP_4DWHBIT_I] & _wRxrHdr[`TLP_PAYBIT_I] & RX_SR_VALID[C_RX_INPUT_STAGES] & _wRxrHdrDelayedSOP);
|
|
|
|
|
|
assign _wRxrHdrHdrLen = {_wRxrHdr[`TLP_4DWHBIT_I],~_wRxrHdr[`TLP_4DWHBIT_I],~_wRxrHdr[`TLP_4DWHBIT_I]};
|
|
assign _wRxrHdrDataSoff = {1'b0,_wRxrHdrSOPStraddle,1'b0} + _wRxrHdrHdrLen;
|
|
assign _wRxrHdrRegSF = RX_SR_SOP[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
|
|
assign _wRxrHdrRegValid = RX_SR_VALID[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
|
|
|
|
assign _wRxrHdr4DWHNoDataSF = _wRxrHdr[`TLP_4DWHBIT_I] & ~_wRxrHdr[`TLP_PAYBIT_I] & _wRxrHdrSOP;
|
|
assign _wRxrHdr4DWHSF = _wRxrHdr4DWHNoDataSF | (_wRxrHdr4DWHWDataSF & _wRxrHdrRegValid);
|
|
assign _wRxrHdr3DWHSF = ~_wRxrHdr[`TLP_4DWHBIT_I] & _wRxrHdrSOP;
|
|
|
|
assign _wRxrHdrSF = (_wRxrHdr3DWHSF | _wRxrHdr4DWHSF | _wRxrHdrSOPStraddle);
|
|
assign _wRxrHdrEF = RX_SR_EOP[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
|
|
|
|
assign _wRxrHdrDataEoff = RX_SR_END_OFFSET[(C_RX_INPUT_STAGES+C_RX_HDR_STAGES)*`SIG_OFFSET_W +: C_OFFSET_WIDTH];
|
|
assign _wRxrHdrSCP = _wRxrHdrSF & _wRxrHdrEF & (_wRxrHdr[`TLP_TYPE_R] == `TLP_TYPE_REQ);
|
|
assign _wRxrHdrMCP = (_wRxrHdrSF & ~_wRxrHdrEF & (_wRxrHdr[`TLP_TYPE_R] == `TLP_TYPE_REQ)) |
|
|
(wRxrHdrMCP & ~wRxrHdrEF);
|
|
|
|
assign _wRxrHdrStartMask = 4'hf << (_wRxrHdrSF ? _wRxrHdrDataSoff[1:0] : 0);
|
|
|
|
assign wRxrDataWordEnable = wRxrHdrEndMask & wRxrHdrStartMask & {4{wRxrDataValid}};
|
|
assign wRxrDataValid = wRxrHdrSCP | wRxrHdrMCP;
|
|
assign wRxrDataStartFlag = wRxrHdrSF;
|
|
assign wRxrDataEndFlag = wRxrHdrEF;
|
|
assign wRxrDataStartOffset = wRxrHdrDataSoff;
|
|
assign wRxrMetaFdwbe = wRxrHdr[`TLP_REQFBE_R];
|
|
assign wRxrMetaLdwbe = wRxrHdr[`TLP_REQLBE_R];
|
|
assign wRxrMetaTC = wRxrHdr[`TLP_TC_R];
|
|
assign wRxrMetaAttr = {wRxrHdr[`TLP_ATTR1_R], wRxrHdr[`TLP_ATTR0_R]};
|
|
assign wRxrMetaTag = wRxrHdr[`TLP_REQTAG_R];
|
|
assign wRxrMetaAddr = wRxrHdr[`TLP_REQADDRDW0_I +: `TLP_REQADDR_W];/* TODO: REQADDR_R*/
|
|
assign wRxrMetaRequesterId = wRxrHdr[`TLP_REQREQID_R];
|
|
assign wRxrMetaLength = wRxrHdr[`TLP_LEN_R];
|
|
assign wRxrMetaEP = wRxrHdr[`TLP_EP_R];
|
|
assign wRxrMetaType = tlp_to_trellis_type({wRxrHdr[`TLP_FMT_R],wRxrHdr[`TLP_TYPE_R]});
|
|
|
|
assign RXR_DATA = RX_SR_DATA[C_PCI_DATA_WIDTH*C_TOTAL_STAGES +: C_PCI_DATA_WIDTH];
|
|
assign RXR_DATA_END_OFFSET = RX_SR_END_OFFSET[`SIG_OFFSET_W*(C_TOTAL_STAGES) +: C_OFFSET_WIDTH];
|
|
|
|
always @(posedge CLK) begin
|
|
rStraddledSOP <= __wRxrHdrSOPStraddle;
|
|
// Set Straddled SOP Split when there is a straddled packet where the
|
|
// header is not contiguous. (Not sure if this is ever possible, but
|
|
// better safe than sorry assert Straddled SOP Split. See Virtex 6 PCIe
|
|
// errata.
|
|
if(__wRxrHdrSOP | RST_IN) begin
|
|
rStraddledSOPSplit <=0;
|
|
end else begin
|
|
rStraddledSOPSplit <= (__wRxrHdrSOPStraddle | rStraddledSOPSplit) & ~RX_SR_VALID[C_RX_INPUT_STAGES];
|
|
end
|
|
end
|
|
|
|
mux
|
|
#(
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// Parameters
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.C_NUM_INPUTS (2),
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.C_CLOG_NUM_INPUTS (1),
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.C_WIDTH (`TLP_MAXHDR_W),
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.C_MUX_TYPE ("SELECT")
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/*AUTOINSTPARAM*/)
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hdr_mux
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(
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// Outputs
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.MUX_OUTPUT (__wRxrHdr[`TLP_MAXHDR_W-1:0]),
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// Inputs
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.MUX_INPUTS ({__wRxrHdrStraddled[`TLP_MAXHDR_W-1:0],
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__wRxrHdrNotStraddled[`TLP_MAXHDR_W-1:0]}),
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.MUX_SELECT (rStraddledSOP | rStraddledSOPSplit)
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/*AUTOINST*/);
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register
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#(
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// Parameters
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.C_WIDTH (64 + 1),
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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hdr_register_63_0
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(
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// Outputs
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.RD_DATA ({_wRxrHdr[C_STRADDLE_W-1:0], _wRxrHdrValid}),
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// Inputs
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.WR_DATA ({__wRxrHdr[C_STRADDLE_W-1:0], __wRxrHdrValid}),
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.WR_EN (__wRxrHdrSOP | rStraddledSOP),
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.RST_IN (RST_IN), // TODO: Remove
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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register
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#(
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// Parameters
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.C_WIDTH (3),
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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sf4dwh
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(
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// Outputs
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.RD_DATA ({_wRxrHdr4DWHWDataSF, _wRxrHdrSOPStraddle,_wRxrHdrSOP}),
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// Inputs
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.WR_DATA ({__wRxrHdr4DWHWDataSF,rStraddledSOP,__wRxrHdrSOP}),
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.WR_EN (1),
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.RST_IN (RST_IN), // TODO: Remove
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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register
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#(
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// Parameters
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.C_WIDTH (1),
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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delayed_sop
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(
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// Outputs
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.RD_DATA ({_wRxrHdrDelayedSOP}),
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// Inputs
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.WR_DATA ({__wRxrHdrSOP}),
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.WR_EN (RX_SR_VALID[C_RX_INPUT_STAGES]),
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.RST_IN (RST_IN), // TODO: Remove
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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register
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#(
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// Parameters
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.C_WIDTH (64),
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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hdr_register_127_64
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(
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// Outputs
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.RD_DATA (_wRxrHdr[`TLP_MAXHDR_W-1:C_STRADDLE_W]),
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// Inputs
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.WR_DATA (__wRxrHdr[`TLP_MAXHDR_W-1:C_STRADDLE_W]),
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.WR_EN (__wRxrHdrSOP | rStraddledSOP | rStraddledSOPSplit), // Non straddled start, Straddled, or straddled split
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.RST_IN (RST_IN), // TODO: Remove
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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// ----- Computation Register -----
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register
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#(
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// Parameters
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.C_WIDTH (64 + 4),/* TODO: TLP_METADATA_W*/
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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metadata
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(// Outputs
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.RD_DATA ({wRxrHdr[`TLP_REQMETADW0_I +: 64],
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wRxrHdrSF,wRxrHdrDataSoff,
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wRxrHdrEF}),/* TODO: TLP_METADATA_R and other signals*/
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// Inputs
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.RST_IN (0),/* TODO: Never need to reset?*/
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.WR_DATA ({_wRxrHdr[`TLP_REQMETADW0_I +: 64],
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_wRxrHdrSF,_wRxrHdrDataSoff[1:0],
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_wRxrHdrEF}),/* TODO: TLP_METADATA_R*/
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.WR_EN (1),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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register
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#(
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// Parameters
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.C_WIDTH (3+8),
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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metadata_valid
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(// Output
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.RD_DATA ({wRxrHdrValid,
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wRxrHdrSCP, wRxrHdrMCP,
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wRxrHdrEndMask, wRxrHdrStartMask}),
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// Inputs
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.RST_IN (RST_IN),
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.WR_DATA ({_wRxrHdrValid,
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_wRxrHdrSCP, _wRxrHdrMCP,
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_wRxrHdrEndMask, _wRxrHdrStartMask}),
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.WR_EN (1),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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register
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#(
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// Parameters
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.C_WIDTH (`SIG_ADDR_W/2),
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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addr_63_32
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(// Outputs
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.RD_DATA (wRxrHdr[`TLP_REQADDRHI_R]),
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// Inputs
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.RST_IN (~_wRxrHdr[`TLP_4DWHBIT_I]),
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.WR_DATA (_wRxrHdr[`TLP_REQADDRLO_R]), // Instead of a mux, we'll use the reset
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.WR_EN (1),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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|
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register
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#(
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// Parameters
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.C_WIDTH (`SIG_ADDR_W/2),
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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addr_31_0
|
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(// Outputs
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.RD_DATA (wRxrHdr[`TLP_REQADDRLO_R]),
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// Inputs
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.RST_IN (0),// Never need to reset
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.WR_DATA (_wRxrHdr[`TLP_4DWHBIT_I] ? _wRxrHdr[`TLP_REQADDRHI_R] : _wRxrHdr[`TLP_REQADDRLO_R]),
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.WR_EN (1),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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offset_to_mask
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#(// Parameters
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.C_MASK_SWAP (0),
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.C_MASK_WIDTH (4)
|
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/*AUTOINSTPARAM*/)
|
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o2m_ef
|
|
(
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// Outputs
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.MASK (_wRxrHdrEndMask),
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// Inputs
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.OFFSET_ENABLE (_wRxrHdrEF),
|
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.OFFSET (_wRxrHdrDataEoff)
|
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/*AUTOINST*/);
|
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pipeline
|
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#(
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// Parameters
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.C_DEPTH (C_RX_OUTPUT_STAGES),
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.C_WIDTH (C_OUTPUT_STAGE_WIDTH),// TODO:
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.C_USE_MEMORY (0)
|
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/*AUTOINSTPARAM*/)
|
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output_pipeline
|
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(
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// Outputs
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.WR_DATA_READY (), // Pinned to 1
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.RD_DATA ({RXR_DATA_WORD_ENABLE, RXR_DATA_START_FLAG, RXR_DATA_START_OFFSET,
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RXR_DATA_END_FLAG,
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RXR_META_FDWBE, RXR_META_LDWBE, RXR_META_TC,
|
|
RXR_META_ATTR, RXR_META_TAG, RXR_META_TYPE,
|
|
RXR_META_ADDR, RXR_META_BAR_DECODED, RXR_META_REQUESTER_ID,
|
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RXR_META_LENGTH, RXR_META_EP}),
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.RD_DATA_VALID (RXR_DATA_VALID),
|
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// Inputs
|
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.WR_DATA ({wRxrDataWordEnable, wRxrDataStartFlag, wRxrDataStartOffset,
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wRxrDataEndFlag,
|
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wRxrMetaFdwbe, wRxrMetaLdwbe, wRxrMetaTC,
|
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wRxrMetaAttr, wRxrMetaTag, wRxrMetaType,
|
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wRxrMetaAddr, wRxrMetaBarDecoded, wRxrMetaRequesterId,
|
|
wRxrMetaLength, wRxrMetaEP}),
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.WR_DATA_VALID (wRxrDataValid),
|
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.RD_DATA_READY (1'b1),
|
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/*AUTOINST*/
|
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// Inputs
|
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.CLK (CLK),
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.RST_IN (RST_IN));
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endmodule
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// Local Variables:
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// verilog-library-directories:("." "../../../common")
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// End:
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