mirror of
https://github.com/KastnerRG/riffa.git
synced 2025-01-30 23:02:54 +08:00
ad496b4c94
The majority of this work can be summarized as: Makefiles have been added to generate all of the boards, boards for each vendor, board, and projects for each board. To make things cleaner I renamed a few of the Xilinx projects, and may rename the latera projects for consistency. I removed the de5_qsys directory, and moved all projects into the de5 directory, but those projects have a Q between DE5 and the PCIe specifications, ie DE5QGen... (haven't updated the documentation) Added c4dev board (untested) Apologies to those of you who recently switched onto the DEVEL branch.
19 lines
477 B
Makefile
19 lines
477 B
Makefile
VENDOR:=xilinx
|
|
ULTRASCALE:=NetFPGA adm7V3 kcu105 vc709 vcu108
|
|
CLASSIC:=ac701 kc705 vc707 zc706
|
|
CURRENT_PATH := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
|
|
RIFFA_PATH=$(CURRENT_PATH)/../riffa_hdl
|
|
|
|
all: $(VENDOR)
|
|
|
|
classic:$(CLASSIC)
|
|
ultrascale:$(ULTRASCALE)
|
|
|
|
$(VENDOR): $(CLASSIC) $(ULTRASCALE)
|
|
$(CLASSIC) $(ULTRASCALE)::
|
|
$(MAKE) -C $@ $(MAKECMDGOALS) RIFFA_PATH=$(RIFFA_PATH)
|
|
|
|
.PHONY:clean $(SUBDIRS)
|
|
clean: $(SUBDIRS) $(VENDOR)
|
|
rm -rf *.log *.jou .Xil *~
|