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https://github.com/KastnerRG/riffa.git
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ad496b4c94
The majority of this work can be summarized as: Makefiles have been added to generate all of the boards, boards for each vendor, board, and projects for each board. To make things cleaner I renamed a few of the Xilinx projects, and may rename the latera projects for consistency. I removed the de5_qsys directory, and moved all projects into the de5 directory, but those projects have a Q between DE5 and the PCIe specifications, ie DE5QGen... (haven't updated the documentation) Added c4dev board (untested) Apologies to those of you who recently switched onto the DEVEL branch.
33 lines
1.2 KiB
Makefile
33 lines
1.2 KiB
Makefile
BOARD_HDL:= $(BOARD_PATH)/riffa_wrapper_$(BOARD).v
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PROJECT_IP=
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PROJECT_HDL=hdl/$(PROJECT).v $(BOARD_HDL) $(patsubst %, $(RIFFA_PATH)/%,$(RIFFA_HDL)) $(PROJECT_FILES)
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PROJECT_CONSTR=constr/$(PROJECT).xdc
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PROJECT_FILE=prj/$(PROJECT).xpr
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PROJECT_FILES=$(PROJECT_IP) $(PROJECT_CONSTR) $(PROJECT_QSRCS) $(PROJECT_HDL)
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.PHONY:$(PROJECT)
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$(PROJECT): bit/$(PROJECT).bit
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@echo Compiling Project $@
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bit/$(PROJECT).bit: $($(PROJECT)_FILES)
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echo "launch_runs impl_1 -to_step write_bitstream -jobs $(JOBS); wait_on_run impl_1" | vivado -mode tcl prj/$(PROJECT).xpr
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mv prj/$(PROJECT).runs/impl_1/$(PROJECT).bit bit/
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synthesis: prj/$(PROJECT).runs/synth_1
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prj/$(PROJECT).runs/synth_1: $($(PROJECT)_FILES)
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echo "launch_runs synth_1 -jobs $(JOBS); wait_on_run synth_1" | vivado -mode tcl prj/$(PROJECT).xpr
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implementation:prj/$(PROJECT).runs/impl_1
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prj/$(PROJECT).runs/impl_1: $($(PROJECT)_FILES)
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echo "launch_runs impl_1 -jobs $(JOBS); wait_on_run impl1" | vivado -mode tcl prj/$(PROJECT).xpr
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all:$(PROJECT)
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clean:
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rm -rf *.log *.jou *~ .Xil
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rm -rf ip/doc ip/sim ip/source ip/synth ip/*.dcp ip/*.v ip/*.xml ip/*.vhdl ip/*.veo ip/*~
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rm -rf prj/*.hw prj/*.runs prj/*.cache prj/*~
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clean-bit:
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rm -rf bit/*.bit
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