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ad496b4c94
The majority of this work can be summarized as: Makefiles have been added to generate all of the boards, boards for each vendor, board, and projects for each board. To make things cleaner I renamed a few of the Xilinx projects, and may rename the latera projects for consistency. I removed the de5_qsys directory, and moved all projects into the de5 directory, but those projects have a Q between DE5 and the PCIe specifications, ie DE5QGen... (haven't updated the documentation) Added c4dev board (untested) Apologies to those of you who recently switched onto the DEVEL branch.
492 lines
27 KiB
Verilog
492 lines
27 KiB
Verilog
// ----------------------------------------------------------------------
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// Copyright (c) 2015, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Filename: KCU105Gen3x4If128.v
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// Version: 1.00.a
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// Verilog Standard: Verilog-2001
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// Description: Top level module for RIFFA 2.2 reference design for the
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// the Xilinx KCU105 Development Board.
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// Author: Dustin Richmond (@darichmond)
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//-----------------------------------------------------------------------------
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`include "functions.vh"
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`include "riffa.vh"
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`include "ultrascale.vh"
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`timescale 1ps / 1ps
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module KCU105_Gen3x4If128
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#(// Number of RIFFA Channels
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parameter C_NUM_CHNL = 1,
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// Number of PCIe Lanes
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parameter C_NUM_LANES = 4,
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// Settings from Vivado IP Generator
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parameter C_PCI_DATA_WIDTH = 128,
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parameter C_MAX_PAYLOAD_BYTES = 256,
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parameter C_LOG_NUM_TAGS = 6)
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(output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP,
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output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN,
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input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXP,
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input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXN,
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output [7:0] LED,
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input PCIE_REFCLK_P,
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input PCIE_REFCLK_N,
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input PCIE_RESET_N);
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// Clocks, etc
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wire user_lnk_up;
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wire user_clk;
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wire user_reset;
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wire pcie_refclk;
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wire pcie_refclk_by2;
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wire pcie_reset_n;
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// Interface: RQ (TXC)
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wire s_axis_rq_tlast;
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wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata;
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wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser;
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wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep;
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wire s_axis_rq_tready;
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wire s_axis_rq_tvalid;
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// Interface: RC (RXC)
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wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata;
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wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser;
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wire m_axis_rc_tlast;
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wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep;
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wire m_axis_rc_tvalid;
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wire m_axis_rc_tready;
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// Interface: CQ (RXR)
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wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata;
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wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser;
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wire m_axis_cq_tlast;
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wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep;
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wire m_axis_cq_tvalid;
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wire m_axis_cq_tready;
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// Interface: CC (TXC)
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wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata;
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wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser;
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wire s_axis_cc_tlast;
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wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep;
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wire s_axis_cc_tvalid;
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wire s_axis_cc_tready;
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// Configuration (CFG) Interface
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wire [3:0] pcie_rq_seq_num;
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wire pcie_rq_seq_num_vld;
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wire [5:0] pcie_rq_tag;
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wire pcie_rq_tag_vld;
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wire pcie_cq_np_req;
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wire [5:0] pcie_cq_np_req_count;
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wire cfg_phy_link_down;
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wire [3:0] cfg_negotiated_width; // CONFIG_LINK_WIDTH
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wire [2:0] cfg_current_speed; // CONFIG_LINK_RATE
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wire [2:0] cfg_max_payload; // CONFIG_MAX_PAYLOAD
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wire [2:0] cfg_max_read_req; // CONFIG_MAX_READ_REQUEST
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wire [7:0] cfg_function_status; // [2] = CONFIG_BUS_MASTER_ENABLE
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wire [5:0] cfg_function_power_state; // Ignorable but not removable
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wire [11:0] cfg_vf_status; // Ignorable but not removable
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wire [17:0] cfg_vf_power_state; // Ignorable but not removable
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wire [1:0] cfg_link_power_state; // Ignorable but not removable
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// Error Reporting Interface
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wire cfg_err_cor_out;
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wire cfg_err_nonfatal_out;
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wire cfg_err_fatal_out;
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wire cfg_ltr_enable;
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wire [5:0] cfg_ltssm_state;
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wire [1:0] cfg_rcb_status;
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wire [1:0] cfg_dpa_substate_change;
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wire [1:0] cfg_obff_enable;
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wire cfg_pl_status_change;
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wire [1:0] cfg_tph_requester_enable;
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wire [5:0] cfg_tph_st_mode;
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wire [5:0] cfg_vf_tph_requester_enable;
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wire [17:0] cfg_vf_tph_st_mode;
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wire [7:0] cfg_fc_ph;
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wire [11:0] cfg_fc_pd;
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wire [7:0] cfg_fc_nph;
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wire [11:0] cfg_fc_npd;
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wire [7:0] cfg_fc_cplh;
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wire [11:0] cfg_fc_cpld;
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wire [2:0] cfg_fc_sel;
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// Interrupt Interface Signals
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wire [3:0] cfg_interrupt_int;
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wire [1:0] cfg_interrupt_pending;
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wire cfg_interrupt_sent;
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wire [1:0] cfg_interrupt_msi_enable;
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wire [5:0] cfg_interrupt_msi_vf_enable;
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wire [5:0] cfg_interrupt_msi_mmenable;
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wire cfg_interrupt_msi_mask_update;
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wire [31:0] cfg_interrupt_msi_data;
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wire [3:0] cfg_interrupt_msi_select;
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wire [31:0] cfg_interrupt_msi_int;
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wire [63:0] cfg_interrupt_msi_pending_status;
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wire cfg_interrupt_msi_sent;
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wire cfg_interrupt_msi_fail;
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wire [2:0] cfg_interrupt_msi_attr;
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wire cfg_interrupt_msi_tph_present;
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wire [1:0] cfg_interrupt_msi_tph_type;
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wire [8:0] cfg_interrupt_msi_tph_st_tag;
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wire [2:0] cfg_interrupt_msi_function_number;
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wire rst_out;
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wire [C_NUM_CHNL-1:0] chnl_rx_clk;
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wire [C_NUM_CHNL-1:0] chnl_rx;
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wire [C_NUM_CHNL-1:0] chnl_rx_ack;
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wire [C_NUM_CHNL-1:0] chnl_rx_last;
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wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len;
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wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off;
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wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
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wire [C_NUM_CHNL-1:0] chnl_rx_data_valid;
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wire [C_NUM_CHNL-1:0] chnl_rx_data_ren;
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wire [C_NUM_CHNL-1:0] chnl_tx_clk;
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wire [C_NUM_CHNL-1:0] chnl_tx;
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wire [C_NUM_CHNL-1:0] chnl_tx_ack;
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wire [C_NUM_CHNL-1:0] chnl_tx_last;
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wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len;
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wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off;
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wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
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wire [C_NUM_CHNL-1:0] chnl_tx_data_valid;
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wire [C_NUM_CHNL-1:0] chnl_tx_data_ren;
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genvar chnl;
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IBUF
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#()
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pci_reset_n_ibuf
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(.O(pcie_reset_n),
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.I(PCIE_RESET_N));
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IBUFDS_GTE3
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#()
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refclk_ibuf
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(.O(pcie_refclk),
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.ODIV2(pcie_refclk_by2),
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.I(PCIE_REFCLK_P),
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.CEB(1'b0),
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.IB(PCIE_REFCLK_N));
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OBUF
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#()
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led_0_obuf
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(.O(LED[0]),
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.I(cfg_ltssm_state[0]));
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OBUF
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#()
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led_1_obuf
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(.O(LED[1]),
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.I(cfg_ltssm_state[1]));
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OBUF
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#()
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led_2_obuf
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(.O(LED[2]),
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.I(cfg_ltssm_state[2]));
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OBUF
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#()
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led_3_obuf
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(.O(LED[3]),
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.I(cfg_ltssm_state[3]));
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OBUF
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#()
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led_4_obuf
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(.O(LED[4]),
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.I(cfg_ltssm_state[4]));
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OBUF
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#()
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led_5_obuf
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(.O(LED[5]),
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.I(cfg_ltssm_state[5]));
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OBUF
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#()
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led_6_obuf
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(.O(LED[6]),
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.I(user_reset));
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OBUF
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#()
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led_7_obuf
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(.O(LED[7]),
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.I(rst_out));
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// Core Top Level Wrapper
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PCIeGen3x4If128
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#()
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pcie3_7x_0_i
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(//---------------------------------------------------------------------
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// PCI Express (pci_exp) Interface
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//---------------------------------------------------------------------
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.pci_exp_txn ( PCI_EXP_TXN ),
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.pci_exp_txp ( PCI_EXP_TXP ),
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.pci_exp_rxn ( PCI_EXP_RXN ),
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.pci_exp_rxp ( PCI_EXP_RXP ),
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//---------------------------------------------------------------------
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// AXI Interface
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//---------------------------------------------------------------------
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.user_clk ( user_clk ),
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.user_reset ( user_reset ),
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.user_lnk_up ( user_lnk_up ),
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.s_axis_rq_tlast ( s_axis_rq_tlast ),
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.s_axis_rq_tdata ( s_axis_rq_tdata ),
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.s_axis_rq_tuser ( s_axis_rq_tuser ),
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.s_axis_rq_tkeep ( s_axis_rq_tkeep ),
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.s_axis_rq_tready ( s_axis_rq_tready ),
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.s_axis_rq_tvalid ( s_axis_rq_tvalid ),
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.m_axis_rc_tdata ( m_axis_rc_tdata ),
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.m_axis_rc_tuser ( m_axis_rc_tuser ),
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.m_axis_rc_tlast ( m_axis_rc_tlast ),
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.m_axis_rc_tkeep ( m_axis_rc_tkeep ),
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.m_axis_rc_tvalid ( m_axis_rc_tvalid ),
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.m_axis_rc_tready ( {22{m_axis_rc_tready}} ),
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.m_axis_cq_tdata ( m_axis_cq_tdata ),
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.m_axis_cq_tuser ( m_axis_cq_tuser ),
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.m_axis_cq_tlast ( m_axis_cq_tlast ),
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.m_axis_cq_tkeep ( m_axis_cq_tkeep ),
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.m_axis_cq_tvalid ( m_axis_cq_tvalid ),
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.m_axis_cq_tready ( {22{m_axis_cq_tready}} ),
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.s_axis_cc_tdata ( s_axis_cc_tdata ),
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.s_axis_cc_tuser ( s_axis_cc_tuser ),
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.s_axis_cc_tlast ( s_axis_cc_tlast ),
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.s_axis_cc_tkeep ( s_axis_cc_tkeep ),
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.s_axis_cc_tvalid ( s_axis_cc_tvalid ),
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.s_axis_cc_tready ( s_axis_cc_tready ),
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//---------------------------------------------------------------------
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// Configuration (CFG) Interface
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//---------------------------------------------------------------------
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.pcie_rq_seq_num ( pcie_rq_seq_num ),
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.pcie_rq_seq_num_vld ( pcie_rq_seq_num_vld ),
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.pcie_rq_tag ( pcie_rq_tag ),
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.pcie_rq_tag_vld ( pcie_rq_tag_vld ),
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.pcie_cq_np_req ( pcie_cq_np_req ),
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.pcie_cq_np_req_count ( pcie_cq_np_req_count ),
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.cfg_phy_link_down ( cfg_phy_link_down ),
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.cfg_phy_link_status ( cfg_phy_link_status),
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.cfg_negotiated_width ( cfg_negotiated_width ),
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.cfg_current_speed ( cfg_current_speed ),
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.cfg_max_payload ( cfg_max_payload ),
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.cfg_max_read_req ( cfg_max_read_req ),
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.cfg_function_status ( cfg_function_status ),
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.cfg_function_power_state ( cfg_function_power_state ),
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.cfg_vf_status ( cfg_vf_status ),
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.cfg_vf_power_state ( cfg_vf_power_state ),
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.cfg_link_power_state ( cfg_link_power_state ),
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// Error Reporting Interface
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.cfg_err_cor_out ( cfg_err_cor_out ),
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.cfg_err_nonfatal_out ( cfg_err_nonfatal_out ),
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.cfg_err_fatal_out ( cfg_err_fatal_out ),
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.cfg_ltr_enable ( cfg_ltr_enable ),
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.cfg_ltssm_state ( cfg_ltssm_state ),
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.cfg_rcb_status ( cfg_rcb_status ),
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.cfg_dpa_substate_change ( cfg_dpa_substate_change ),
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.cfg_obff_enable ( cfg_obff_enable ),
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.cfg_pl_status_change ( cfg_pl_status_change ),
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.cfg_tph_requester_enable ( cfg_tph_requester_enable ),
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.cfg_tph_st_mode ( cfg_tph_st_mode ),
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.cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ),
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.cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ),
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.cfg_fc_ph ( cfg_fc_ph ),
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.cfg_fc_pd ( cfg_fc_pd ),
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.cfg_fc_nph ( cfg_fc_nph ),
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.cfg_fc_npd ( cfg_fc_npd ),
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.cfg_fc_cplh ( cfg_fc_cplh ),
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.cfg_fc_cpld ( cfg_fc_cpld ),
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.cfg_fc_sel ( cfg_fc_sel ),
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//---------------------------------------------------------------------
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// EP Only
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//---------------------------------------------------------------------
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// Interrupt Interface Signals
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.cfg_interrupt_int ( cfg_interrupt_int ),
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.cfg_interrupt_pending ( cfg_interrupt_pending ),
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.cfg_interrupt_sent ( cfg_interrupt_sent ),
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.cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable ),
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.cfg_interrupt_msi_vf_enable ( cfg_interrupt_msi_vf_enable ),
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.cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ),
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.cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ),
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.cfg_interrupt_msi_data ( cfg_interrupt_msi_data ),
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.cfg_interrupt_msi_select ( cfg_interrupt_msi_select ),
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.cfg_interrupt_msi_int ( cfg_interrupt_msi_int ),
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.cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_pending_status ),
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.cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ),
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.cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ),
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.cfg_interrupt_msi_attr ( cfg_interrupt_msi_attr ),
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.cfg_interrupt_msi_tph_present ( cfg_interrupt_msi_tph_present ),
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.cfg_interrupt_msi_tph_type ( cfg_interrupt_msi_tph_type ),
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.cfg_interrupt_msi_tph_st_tag ( cfg_interrupt_msi_tph_st_tag ),
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.cfg_interrupt_msi_function_number ( cfg_interrupt_msi_function_number ),
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.cfg_interrupt_msi_pending_status_function_num ( 4'b0),
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.cfg_interrupt_msi_pending_status_data_enable ( 1'b0),
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//--------------------------------------------------------------------------------------//
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// Reset Pass Through Signals
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// - Only used for PCIe_X0Y0
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//--------------------------------------------------------------------------------------//
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.pcie_perstn0_out (pcie_reset_n_core),
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.pcie_perstn1_in (1'b0),
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.pcie_perstn1_out (),
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//---------------------------------------------------------------------
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// System(SYS) Interface
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//---------------------------------------------------------------------
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.sys_clk (pcie_refclk_by2),
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.sys_clk_gt (pcie_refclk),
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.sys_reset (pcie_reset_n));
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riffa_wrapper_kcu105
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#(/*AUTOINSTPARAM*/
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// Parameters
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.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
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.C_NUM_CHNL (C_NUM_CHNL),
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.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
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.C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES))
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riffa
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(// Outputs
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.M_AXIS_CQ_TREADY (m_axis_cq_tready),
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.M_AXIS_RC_TREADY (m_axis_rc_tready),
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.S_AXIS_CC_TVALID (s_axis_cc_tvalid),
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.S_AXIS_CC_TLAST (s_axis_cc_tlast),
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.S_AXIS_CC_TDATA (s_axis_cc_tdata[C_PCI_DATA_WIDTH-1:0]),
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.S_AXIS_CC_TKEEP (s_axis_cc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
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.S_AXIS_CC_TUSER (s_axis_cc_tuser[`SIG_CC_TUSER_W-1:0]),
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.S_AXIS_RQ_TVALID (s_axis_rq_tvalid),
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.S_AXIS_RQ_TLAST (s_axis_rq_tlast),
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.S_AXIS_RQ_TDATA (s_axis_rq_tdata[C_PCI_DATA_WIDTH-1:0]),
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.S_AXIS_RQ_TKEEP (s_axis_rq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
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.S_AXIS_RQ_TUSER (s_axis_rq_tuser[`SIG_RQ_TUSER_W-1:0]),
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.USER_CLK (user_clk),
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.USER_RESET (user_reset),
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.CFG_INTERRUPT_INT (cfg_interrupt_int[3:0]),
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.CFG_INTERRUPT_PENDING (cfg_interrupt_pending[1:0]),
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.CFG_INTERRUPT_MSI_SELECT (cfg_interrupt_msi_select[3:0]),
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.CFG_INTERRUPT_MSI_INT (cfg_interrupt_msi_int[31:0]),
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.CFG_INTERRUPT_MSI_PENDING_STATUS(cfg_interrupt_msi_pending_status[63:0]),
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.CFG_INTERRUPT_MSI_ATTR (cfg_interrupt_msi_attr[2:0]),
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.CFG_INTERRUPT_MSI_TPH_PRESENT (cfg_interrupt_msi_tph_present),
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.CFG_INTERRUPT_MSI_TPH_TYPE (cfg_interrupt_msi_tph_type[1:0]),
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.CFG_INTERRUPT_MSI_TPH_ST_TAG (cfg_interrupt_msi_tph_st_tag[8:0]),
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.CFG_INTERRUPT_MSI_FUNCTION_NUMBER(cfg_interrupt_msi_function_number[2:0]),
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.CFG_FC_SEL (cfg_fc_sel[2:0]),
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.PCIE_CQ_NP_REQ (pcie_cq_np_req),
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.RST_OUT (rst_out),
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.CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]),
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.CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]),
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.CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
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.CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
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.CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
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.CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
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.CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]),
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.CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
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// Inputs
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.M_AXIS_CQ_TVALID (m_axis_cq_tvalid),
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.M_AXIS_CQ_TLAST (m_axis_cq_tlast),
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.M_AXIS_CQ_TDATA (m_axis_cq_tdata[C_PCI_DATA_WIDTH-1:0]),
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.M_AXIS_CQ_TKEEP (m_axis_cq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
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.M_AXIS_CQ_TUSER (m_axis_cq_tuser[`SIG_CQ_TUSER_W-1:0]),
|
|
.M_AXIS_RC_TVALID (m_axis_rc_tvalid),
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|
.M_AXIS_RC_TLAST (m_axis_rc_tlast),
|
|
.M_AXIS_RC_TDATA (m_axis_rc_tdata[C_PCI_DATA_WIDTH-1:0]),
|
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.M_AXIS_RC_TKEEP (m_axis_rc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
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|
.M_AXIS_RC_TUSER (m_axis_rc_tuser[`SIG_RC_TUSER_W-1:0]),
|
|
.S_AXIS_CC_TREADY (s_axis_cc_tready),
|
|
.S_AXIS_RQ_TREADY (s_axis_rq_tready),
|
|
.CFG_INTERRUPT_MSI_ENABLE (cfg_interrupt_msi_enable[1:0]),
|
|
.CFG_INTERRUPT_MSI_MASK_UPDATE (cfg_interrupt_msi_mask_update),
|
|
.CFG_INTERRUPT_MSI_DATA (cfg_interrupt_msi_data[31:0]),
|
|
.CFG_INTERRUPT_MSI_SENT (cfg_interrupt_msi_sent),
|
|
.CFG_INTERRUPT_MSI_FAIL (cfg_interrupt_msi_fail),
|
|
.CFG_FC_CPLH (cfg_fc_cplh[7:0]),
|
|
.CFG_FC_CPLD (cfg_fc_cpld[11:0]),
|
|
.CFG_NEGOTIATED_WIDTH (cfg_negotiated_width[3:0]),
|
|
.CFG_CURRENT_SPEED (cfg_current_speed[2:0]),
|
|
.CFG_MAX_PAYLOAD (cfg_max_payload[2:0]),
|
|
.CFG_MAX_READ_REQ (cfg_max_read_req[2:0]),
|
|
.CFG_FUNCTION_STATUS (cfg_function_status[7:0]),
|
|
.CFG_RCB_STATUS (cfg_rcb_status[1:0]),
|
|
.CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]),
|
|
.CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]),
|
|
.CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
|
|
.CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]),
|
|
.CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]),
|
|
.CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]),
|
|
.CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
|
|
.CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
|
|
.CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
|
|
.CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0]));
|
|
|
|
generate
|
|
for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels
|
|
chnl_tester
|
|
#(/*AUTOINSTPARAM*/
|
|
// Parameters
|
|
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH))
|
|
module1
|
|
(.CLK(user_clk),
|
|
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
|
|
// Rx interface
|
|
.CHNL_RX_CLK(chnl_rx_clk[chnl]),
|
|
.CHNL_RX(chnl_rx[chnl]),
|
|
.CHNL_RX_ACK(chnl_rx_ack[chnl]),
|
|
.CHNL_RX_LAST(chnl_rx_last[chnl]),
|
|
.CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]),
|
|
.CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]),
|
|
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]),
|
|
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]),
|
|
.CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]),
|
|
// Tx interface
|
|
.CHNL_TX_CLK(chnl_tx_clk[chnl]),
|
|
.CHNL_TX(chnl_tx[chnl]),
|
|
.CHNL_TX_ACK(chnl_tx_ack[chnl]),
|
|
.CHNL_TX_LAST(chnl_tx_last[chnl]),
|
|
.CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]),
|
|
.CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]),
|
|
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]),
|
|
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]),
|
|
.CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl])
|
|
/*AUTOINST*/);
|
|
end
|
|
endgenerate
|
|
endmodule
|
|
// Local Variables:
|
|
// verilog-library-directories:("../../../../riffa_hdl/" "../../")
|
|
// End:
|
|
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