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80 lines
3.1 KiB
Systemverilog
80 lines
3.1 KiB
Systemverilog
// ----------------------------------------------------------------------
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// Copyright (c) 2016, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Filename: riffa.vh
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// Version: 1.0
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// Verilog Standard: Verilog-2001
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// Description: The riffa.vh file is a header file that defines
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// various RIFFA-specific primitives.
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// Author: Dustin Richmond (@darichmond)
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//-----------------------------------------------------------------------------
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`ifndef __RIFFA_VH
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`define __RIFFA_VH 1
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`include "widths.vh"
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// User Interface Signals
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`define SIG_CHNL_OFFSET_W 31
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`define SIG_CHNL_LENGTH_W 32
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`define SIG_CHNL_LAST_W 1
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// Engine/Channel interface signals
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`define SIG_TXRLEN_W 32
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`define SIG_OFFLAST_W 32
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`define SIG_LAST_W 1
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`define SIG_TXDONELEN_W 32
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`define SIG_RXDONELEN_W 32
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`define SIG_CORESETTINGS_W 32
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// Writable addresses
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`define ADDR_SGRX_LEN 4'b0000
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`define ADDR_SGRX_ADDRLO 4'b0001
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`define ADDR_SGRX_ADDRHI 4'b0010
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`define ADDR_RX_LEN 4'b0011
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`define ADDR_RX_OFFLAST 4'b0100
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`define ADDR_SGTX_LEN 4'b0101
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`define ADDR_SGTX_ADDRLO 4'b0110
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`define ADDR_SGTX_ADDRHI 4'b0111
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// Readable Addresses
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`define ADDR_TX_LEN 4'b1000
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`define ADDR_TX_OFFLAST 4'b1001
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`define ADDR_CORESETTINGS 4'b1010
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`define ADDR_INTR_VECTOR_0 4'b1011
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`define ADDR_INTR_VECTOR_1 4'b1100
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`define ADDR_RX_LEN_XFERD 4'b1101
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`define ADDR_TX_LEN_XFERD 4'b1110
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`define ADDR_FPGA_NAME 4'b1111
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`endif
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