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212 lines
6.3 KiB
Verilog
212 lines
6.3 KiB
Verilog
// ----------------------------------------------------------------------
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// Copyright (c) 2016, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Filename: rx_port_requester.v
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// Version: 1.00.a
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// Verilog Standard: Verilog-2001
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// Description: Issues read requests to the tx_engine for the rx_port
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// and sg_list_requester modules in the rx_port. Expects those modules to update
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// their address and length values after every request issued. Also expects them
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// to update their space available values within 6 cycles of a change to the
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// RX_LEN.
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// Author: Matt Jacobsen
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// History: @mattj: Version 2.0
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//-----------------------------------------------------------------------------
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`define S_RXPORTREQ_RX_TX 2'b00
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`define S_RXPORTREQ_TX_RX 2'b01
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`define S_RXPORTREQ_ISSUE 2'b10
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`timescale 1ns/1ns
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module rx_port_requester_mux (
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input RST,
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input CLK,
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input SG_RX_REQ, // Scatter gather RX read request
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input [9:0] SG_RX_LEN, // Scatter gather RX read request length
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input [63:0] SG_RX_ADDR, // Scatter gather RX read request address
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output SG_RX_REQ_PROC, // Scatter gather RX read request processing
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input SG_TX_REQ, // Scatter gather TX read request
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input [9:0] SG_TX_LEN, // Scatter gather TX read request length
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input [63:0] SG_TX_ADDR, // Scatter gather TX read request address
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output SG_TX_REQ_PROC, // Scatter gather TX read request processing
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input MAIN_REQ, // Main read request
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input [9:0] MAIN_LEN, // Main read request length
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input [63:0] MAIN_ADDR, // Main read request address
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output MAIN_REQ_PROC, // Main read request processing
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output RX_REQ, // Read request
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input RX_REQ_ACK, // Read request accepted
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output [1:0] RX_REQ_TAG, // Read request data tag
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output [63:0] RX_REQ_ADDR, // Read request address
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output [9:0] RX_REQ_LEN, // Read request length
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output REQ_ACK // Request accepted
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);
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reg rRxReqAck=0, _rRxReqAck=0;
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(* syn_encoding = "user" *)
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(* fsm_encoding = "user" *)
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reg [1:0] rState=`S_RXPORTREQ_RX_TX, _rState=`S_RXPORTREQ_RX_TX;
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reg [9:0] rLen=0, _rLen=0;
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reg [63:0] rAddr=64'd0, _rAddr=64'd0;
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reg rSgRxAck=0, _rSgRxAck=0;
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reg rSgTxAck=0, _rSgTxAck=0;
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reg rMainAck=0, _rMainAck=0;
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reg rAck=0, _rAck=0;
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assign SG_RX_REQ_PROC = rSgRxAck;
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assign SG_TX_REQ_PROC = rSgTxAck;
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assign MAIN_REQ_PROC = rMainAck;
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assign RX_REQ = rState[1]; // S_RXPORTREQ_ISSUE
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assign RX_REQ_TAG = {rSgTxAck, rSgRxAck};
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assign RX_REQ_ADDR = rAddr;
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assign RX_REQ_LEN = rLen;
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assign REQ_ACK = rAck;
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// Buffer signals that come from outside the rx_port.
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always @ (posedge CLK) begin
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rRxReqAck <= #1 (RST ? 1'd0 : _rRxReqAck);
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end
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always @ (*) begin
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_rRxReqAck = RX_REQ_ACK;
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end
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// Handle issuing read requests. Scatter gather requests are processed
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// with higher priority than the main channel.
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always @ (posedge CLK) begin
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rState <= #1 (RST ? `S_RXPORTREQ_RX_TX : _rState);
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rLen <= #1 _rLen;
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rAddr <= #1 _rAddr;
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rSgRxAck <= #1 _rSgRxAck;
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rSgTxAck <= #1 _rSgTxAck;
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rMainAck <= #1 _rMainAck;
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rAck <= #1 _rAck;
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end
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always @ (*) begin
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_rState = rState;
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_rLen = rLen;
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_rAddr = rAddr;
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_rSgRxAck = rSgRxAck;
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_rSgTxAck = rSgTxAck;
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_rMainAck = rMainAck;
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_rAck = rAck;
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case (rState)
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`S_RXPORTREQ_RX_TX: begin // Wait for a new read request
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if (SG_RX_REQ) begin
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_rLen = SG_RX_LEN;
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_rAddr = SG_RX_ADDR;
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_rSgRxAck = 1;
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_rAck = 1;
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_rState = `S_RXPORTREQ_ISSUE;
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end
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else if (SG_TX_REQ) begin
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_rLen = SG_TX_LEN;
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_rAddr = SG_TX_ADDR;
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_rSgTxAck = 1;
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_rAck = 1;
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_rState = `S_RXPORTREQ_ISSUE;
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end
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else if (MAIN_REQ) begin
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_rLen = MAIN_LEN;
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_rAddr = MAIN_ADDR;
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_rMainAck = 1;
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_rAck = 1;
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_rState = `S_RXPORTREQ_ISSUE;
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end
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else begin
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_rState = `S_RXPORTREQ_TX_RX;
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end
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end
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`S_RXPORTREQ_TX_RX: begin // Wait for a new read request
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if (SG_TX_REQ) begin
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_rLen = SG_TX_LEN;
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_rAddr = SG_TX_ADDR;
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_rSgTxAck = 1;
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_rAck = 1;
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_rState = `S_RXPORTREQ_ISSUE;
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end
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else if (SG_RX_REQ) begin
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_rLen = SG_RX_LEN;
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_rAddr = SG_RX_ADDR;
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_rSgRxAck = 1;
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_rAck = 1;
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_rState = `S_RXPORTREQ_ISSUE;
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end
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else if (MAIN_REQ) begin
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_rLen = MAIN_LEN;
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_rAddr = MAIN_ADDR;
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_rMainAck = 1;
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_rAck = 1;
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_rState = `S_RXPORTREQ_ISSUE;
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end
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else begin
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_rState = `S_RXPORTREQ_RX_TX;
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end
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end
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`S_RXPORTREQ_ISSUE: begin // Issue the request
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_rAck = 0;
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if (rRxReqAck) begin
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_rSgRxAck = 0;
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_rSgTxAck = 0;
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_rMainAck = 0;
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if (rSgRxAck)
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_rState = `S_RXPORTREQ_TX_RX;
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else
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_rState = `S_RXPORTREQ_RX_TX;
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end
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end
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default: begin
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_rState = `S_RXPORTREQ_RX_TX;
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end
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endcase
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end
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endmodule
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