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505 lines
21 KiB
Verilog
505 lines
21 KiB
Verilog
// ----------------------------------------------------------------------
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// Copyright (c) 2016, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Filename: rxr_engine_classic.v
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// Version: 1.0
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// Verilog Standard: Verilog-2001
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// Description: The RXR Engine (Ultrascale) takes a single stream of
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// AXI packets and provides the completion packets on the RXR Interface.
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// This Engine is capable of operating at "line rate".
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// Author: Dustin Richmond (@darichmond)
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//-----------------------------------------------------------------------------
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`timescale 1ns/1ns
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`include "trellis.vh"
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`include "ultrascale.vh"
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module rxr_engine_ultrascale
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#(parameter C_PCI_DATA_WIDTH = 128,
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parameter C_RX_PIPELINE_DEPTH=10)
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(// Interface: Clocks
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input CLK,
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// Interface: Resets
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input RST_BUS, // Replacement for generic RST_IN
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input RST_LOGIC, // Addition for RIFFA_RST
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output DONE_RXR_RST,
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// Interface: CQ
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input M_AXIS_CQ_TVALID,
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input M_AXIS_CQ_TLAST,
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input [C_PCI_DATA_WIDTH-1:0] M_AXIS_CQ_TDATA,
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input [(C_PCI_DATA_WIDTH/32)-1:0] M_AXIS_CQ_TKEEP,
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input [`SIG_CQ_TUSER_W-1:0] M_AXIS_CQ_TUSER,
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output M_AXIS_CQ_TREADY,
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// Interface: RXR Engine
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output [C_PCI_DATA_WIDTH-1:0] RXR_DATA,
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output RXR_DATA_VALID,
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output [(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_WORD_ENABLE,
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output RXR_DATA_START_FLAG,
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output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET,
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output RXR_DATA_END_FLAG,
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output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET,
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output [`SIG_FBE_W-1:0] RXR_META_FDWBE,
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output [`SIG_LBE_W-1:0] RXR_META_LDWBE,
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output [`SIG_TC_W-1:0] RXR_META_TC,
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output [`SIG_ATTR_W-1:0] RXR_META_ATTR,
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output [`SIG_TAG_W-1:0] RXR_META_TAG,
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output [`SIG_TYPE_W-1:0] RXR_META_TYPE,
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output [`SIG_ADDR_W-1:0] RXR_META_ADDR,
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output [`SIG_BARDECODE_W-1:0] RXR_META_BAR_DECODED,
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output [`SIG_REQID_W-1:0] RXR_META_REQUESTER_ID,
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output [`SIG_LEN_W-1:0] RXR_META_LENGTH,
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output RXR_META_EP
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);
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// Width of the Byte Enable Shift register
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localparam C_RX_BE_W = (`SIG_FBE_W + `SIG_LBE_W);
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localparam C_RX_INPUT_STAGES = 0;
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localparam C_RX_OUTPUT_STAGES = 2; // Should always be at least one
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localparam C_RX_COMPUTATION_STAGES = 1;
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localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES;
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// CYCLE = LOW ORDER BIT (INDEX) / C_PCI_DATA_WIDTH
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localparam C_RX_ADDRDW0_CYCLE = (`UPKT_RXR_ADDRDW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
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localparam C_RX_ADDRDW1_CYCLE = (`UPKT_RXR_ADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
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localparam C_RX_METADW0_CYCLE = (`UPKT_RXR_METADW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
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localparam C_RX_METADW1_CYCLE = (`UPKT_RXR_METADW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
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localparam C_RX_PAYLOAD_CYCLE = (`UPKT_RXR_PAYLOAD_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
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localparam C_RX_BE_CYCLE = C_RX_INPUT_STAGES; // Available on the first cycle (as per the spec)
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localparam C_RX_ADDRDW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_ADDRDW0_I%C_PCI_DATA_WIDTH);
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localparam C_RX_ADDRDW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_ADDRDW1_I%C_PCI_DATA_WIDTH);
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localparam C_RX_METADW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_METADW0_I%C_PCI_DATA_WIDTH);
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localparam C_RX_METADW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_METADW1_I%C_PCI_DATA_WIDTH);
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localparam C_RX_BE_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES;
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// Mask width of the calculated SOF/EOF fields
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localparam C_OFFSET_WIDTH = clog2s(C_PCI_DATA_WIDTH/32);
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wire wMAxisCqSop;
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wire wMAxisCqTlast;
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wire [C_RX_PIPELINE_DEPTH:0] wRxSrSop;
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wire [C_RX_PIPELINE_DEPTH:0] wRxSrEop;
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wire [C_RX_PIPELINE_DEPTH:0] wRxSrDataValid;
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wire [(C_RX_PIPELINE_DEPTH+1)*C_RX_BE_W-1:0] wRxSrBe;
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wire [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] wRxSrData;
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wire wRxrDataValid;
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wire wRxrDataReady; // Pinned High
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wire wRxrDataEndFlag;
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wire [C_OFFSET_WIDTH-1:0] wRxrDataEndOffset;
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wire wRxrDataStartFlag;
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wire [C_OFFSET_WIDTH-1:0] wRxrDataStartOffset;
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wire [(C_PCI_DATA_WIDTH/32)-1:0] wRxrDataWordEnable;
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wire [127:0] wRxrHdr;
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wire [`SIG_TYPE_W-1:0] wRxrType;
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wire [`SIG_FBE_W-1:0] wRxrMetaFdwbe;
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wire [`SIG_LBE_W-1:0] wRxrMetaLdwbe;
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wire [C_RX_BE_W-1:0] wRxrBe;
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wire [`SIG_BARDECODE_W-1:0] wRxrBarDecoded;
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wire [127:0] wHdr;
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wire wEndFlag;
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wire wEndFlagLastCycle;
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wire _wEndFlag;
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wire [C_OFFSET_WIDTH-1:0] wEndOffset;
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wire [(C_PCI_DATA_WIDTH/32)-1:0] wEndMask;
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wire _wStartFlag;
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wire wStartFlag;
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wire [1:0] wStartFlags;
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wire [(C_PCI_DATA_WIDTH/32)-1:0] wStartMask;
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wire [C_OFFSET_WIDTH-1:0] wStartOffset;
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wire [C_RX_BE_W-1:0] wByteEnables;
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wire [`SIG_BARDECODE_W-1:0] wBarDecoded;
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wire wHasPayload;
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wire [`SIG_TYPE_W-1:0] wType;
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reg rValid,_rValid;
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reg rRST;
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assign DONE_RXR_RST = ~rRST;
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assign wMAxisCqSop = M_AXIS_CQ_TUSER[`UPKT_CQ_TUSER_SOP_R];
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assign wMAxisCqTlast = M_AXIS_CQ_TLAST;
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assign wBarDecoded = (8'b0000_0001 << wHdr[`UPKT_RXR_BARID_R]);
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// We assert the end flag on the last cycle of a packet, however on single
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// cycle packets we need to check that there wasn't an end flag last cycle
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// (because wStartFlag will take priority when setting rValid) so we can
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// deassert rValid if necessary.
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assign wEndFlag = wRxSrEop[C_RX_INPUT_STAGES + C_RX_COMPUTATION_STAGES];
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assign wEndFlagLastCycle = wRxSrEop[C_RX_INPUT_STAGES + C_RX_COMPUTATION_STAGES + 1];
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/* verilator lint_off WIDTH */
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assign wStartOffset = 4;
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assign wEndOffset = wHdr[`UPKT_RXR_LENGTH_I +: C_OFFSET_WIDTH] + ((`UPKT_RXR_MAXHDR_W-32)/32);
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/* verilator lint_on WIDTH */
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// Output assignments. See the header file derived from the user
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// guide for indices.
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assign RXR_META_EP = wRxrHdr[`UPKT_RXR_EP_R];
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assign RXR_META_LENGTH = wRxrHdr[`UPKT_RXR_LENGTH_I+:`SIG_LEN_W];// The top three bits are ignored (fine)
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assign RXR_META_ATTR = wRxrHdr[`UPKT_RXR_ATTR_R];
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assign RXR_META_TC = wRxrHdr[`UPKT_RXR_TC_R];
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assign RXR_META_TYPE = wRxrType;
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assign RXR_META_REQUESTER_ID = wRxrHdr[`UPKT_RXR_REQID_R];
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assign RXR_META_TAG = wRxrHdr[`UPKT_RXR_TAG_R];
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assign RXR_META_FDWBE = wRxrMetaFdwbe;
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assign RXR_META_LDWBE = wRxrMetaLdwbe;
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assign RXR_META_ADDR = {wRxrHdr[`UPKT_RXR_ADDR_R],2'b0};
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assign RXR_DATA_START_FLAG = wRxrDataStartFlag;
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assign RXR_DATA_START_OFFSET = 0;
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assign RXR_DATA_END_FLAG = wRxrDataEndFlag;
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assign RXR_DATA_END_OFFSET = wEndOffset;
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assign RXR_META_BAR_DECODED = wRxrBarDecoded;
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assign RXR_DATA_VALID = wRxrDataValid;
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assign RXR_DATA = wRxSrData[(C_TOTAL_STAGES)*C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];
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assign M_AXIS_CQ_TREADY = 1'b1;
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assign wType = upkt_to_trellis_type({wHdr[`UPKT_RXR_TYPE_R], wHdr[`UPKT_RXR_LENGTH_R] != 0});
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assign _wEndFlag = wRxSrEop[C_RX_INPUT_STAGES];
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assign wEndFlag = wRxSrEop[C_RX_INPUT_STAGES+1];
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assign _wStartFlag = wStartFlags != 0;
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assign wHasPayload = ~wType[`TRLS_TYPE_PAY_I];
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assign wStartMask = {C_PCI_DATA_WIDTH/32{1'b1}} << ({C_OFFSET_WIDTH{wStartFlag}}& wStartOffset[C_OFFSET_WIDTH-1:0]);
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generate
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if(C_PCI_DATA_WIDTH == 64) begin
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assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 2] & ~rValid;
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assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wRxSrEop[C_RX_INPUT_STAGES]; // No Payload
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end else if (C_PCI_DATA_WIDTH == 128) begin
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assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 1] & ~rValid;
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assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES] & wRxSrEop[C_RX_INPUT_STAGES]; // No Payload
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end else begin // 256
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assign wStartFlags[1] = 0;
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assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES];
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end // else: !if(C_PCI_DATA_WIDTH == 128)
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endgenerate
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always @(*) begin
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_rValid = rValid;
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if(_wStartFlag) begin
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_rValid = 1'b1;
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end else if (wEndFlag) begin
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_rValid = 1'b0;
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end
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end
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always @(posedge CLK) begin
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if(rRST) begin
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rValid <= 1'b0;
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end else begin
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rValid <= _rValid;
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end
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end
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always @(posedge CLK) begin
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rRST <= RST_BUS | RST_LOGIC;
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end
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register
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#(// Parameters
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.C_WIDTH (32),
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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meta_DW1_register
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(// Outputs
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.RD_DATA (wHdr[127:96]),
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// Inputs
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.RST_IN (0),
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.WR_DATA (wRxSrData[C_RX_METADW1_INDEX +: 32]),
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.WR_EN (wRxSrSop[C_RX_METADW1_CYCLE]),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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register
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#(// Parameters
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.C_WIDTH (32),
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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metadata_DW0_register
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(// Outputs
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.RD_DATA (wHdr[95:64]),
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// Inputs
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.RST_IN (0),
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.WR_DATA (wRxSrData[C_RX_METADW0_INDEX +: 32]),
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.WR_EN (wRxSrSop[C_RX_METADW0_CYCLE]),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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register
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#(// Parameters
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.C_WIDTH (32),
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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addr_DW1_register
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(// Outputs
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.RD_DATA (wHdr[63:32]),
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// Inputs
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.RST_IN (0),
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.WR_DATA (wRxSrData[C_RX_ADDRDW1_INDEX +: 32]),
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.WR_EN (wRxSrSop[C_RX_ADDRDW1_CYCLE]),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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register
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#(// Parameters
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.C_WIDTH (32),
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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addr_DW0_register
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(// Outputs
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.RD_DATA (wHdr[31:0]),
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// Inputs
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.RST_IN (0),
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.WR_DATA (wRxSrData[C_RX_ADDRDW0_INDEX +: 32]),
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.WR_EN (wRxSrSop[C_RX_ADDRDW0_CYCLE]),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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register
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#(// Parameters
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.C_WIDTH (C_RX_BE_W),
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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be_register
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(// Outputs
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.RD_DATA (wByteEnables),
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// Inputs
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.RST_IN (0),
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.WR_DATA (wRxSrBe[C_RX_BE_INDEX +: C_RX_BE_W]),
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.WR_EN (wRxSrSop[C_RX_BE_CYCLE]),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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// Shift register for input data with output taps for each delayed
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// cycle.
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shiftreg
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#(// Parameters
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.C_DEPTH (C_RX_PIPELINE_DEPTH),
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.C_WIDTH (C_PCI_DATA_WIDTH),
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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data_shiftreg_inst
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(// Outputs
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.RD_DATA (wRxSrData),
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// Inputs
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.WR_DATA (M_AXIS_CQ_TDATA),
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.RST_IN (0),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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// Start Flag Shift Register. Data enables are derived from the
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// taps on this shift register.
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shiftreg
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#(// Parameters
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.C_DEPTH (C_RX_PIPELINE_DEPTH),
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.C_WIDTH (1'b1),
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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sop_shiftreg_inst
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(// Outputs
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.RD_DATA (wRxSrSop),
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// Inputs
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.WR_DATA (wMAxisCqSop & M_AXIS_CQ_TVALID),
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.RST_IN (0),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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// End Flag Shift Register.
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shiftreg
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#(// Parameters
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.C_DEPTH (C_RX_PIPELINE_DEPTH),
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.C_WIDTH (1'b1),
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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eop_shiftreg_inst
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(// Outputs
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.RD_DATA (wRxSrEop),
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// Inputs
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.WR_DATA (wMAxisCqTlast),
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.RST_IN (0),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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// Data Valid Shift Register. Data enables are derived from the
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// taps on this shift register.
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shiftreg
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#(// Parameters
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.C_DEPTH (C_RX_PIPELINE_DEPTH),
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.C_WIDTH (1'b1),
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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valid_shiftreg_inst
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(// Outputs
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.RD_DATA (wRxSrDataValid),
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// Inputs
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.WR_DATA (M_AXIS_CQ_TVALID),
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.RST_IN (rRst),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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// Shift register for input data with output taps for each delayed
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// cycle.
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shiftreg
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#(// Parameters
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.C_DEPTH (C_RX_PIPELINE_DEPTH),
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.C_WIDTH (C_RX_BE_W),
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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be_shiftreg_inst
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(// Outputs
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.RD_DATA (wRxSrBe),
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// Inputs
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.WR_DATA (M_AXIS_CQ_TUSER[`UPKT_CQ_TUSER_BE_R]),
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.RST_IN (0),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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register
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#(// Parameters
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.C_WIDTH (1),
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.C_VALUE (1'b0)
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/*AUTOINSTPARAM*/)
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start_flag_register
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(// Outputs
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.RD_DATA (wStartFlag),
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// Inputs
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.WR_DATA (_wStartFlag),
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.WR_EN (1),
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.RST_IN (0),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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offset_to_mask
|
|
#(// Parameters
|
|
.C_MASK_SWAP (0),
|
|
.C_MASK_WIDTH (C_PCI_DATA_WIDTH/32)
|
|
/*AUTOINSTPARAM*/)
|
|
o2m_ef
|
|
(// Outputs
|
|
.MASK (wEndMask),
|
|
// Inputs
|
|
.OFFSET_ENABLE (wEndFlag),
|
|
.OFFSET (wEndOffset)
|
|
/*AUTOINST*/);
|
|
|
|
generate
|
|
if(C_RX_OUTPUT_STAGES == 0) begin
|
|
assign RXR_DATA_WORD_ENABLE = {wEndMask & wStartMask} & {C_PCI_DATA_WIDTH/32{~rValid | wHasPayload}};
|
|
end else begin
|
|
register
|
|
#(// Parameters
|
|
.C_WIDTH (C_PCI_DATA_WIDTH/32),
|
|
.C_VALUE (0)
|
|
/*AUTOINSTPARAM*/)
|
|
dw_enable
|
|
(// Outputs
|
|
.RD_DATA (wRxrDataWordEnable),
|
|
// Inputs
|
|
.RST_IN (~rValid | wHasPayload),
|
|
.WR_DATA (wEndMask & wStartMask),
|
|
.WR_EN (1),
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.CLK (CLK));
|
|
|
|
pipeline
|
|
#(// Parameters
|
|
.C_DEPTH (C_RX_OUTPUT_STAGES-1),
|
|
.C_WIDTH (C_PCI_DATA_WIDTH/32),
|
|
.C_USE_MEMORY (0)
|
|
/*AUTOINSTPARAM*/)
|
|
dw_pipeline
|
|
(// Outputs
|
|
.WR_DATA_READY (), // Pinned to 1
|
|
.RD_DATA (RXR_DATA_WORD_ENABLE),
|
|
.RD_DATA_VALID (),
|
|
// Inputs
|
|
.WR_DATA (wRxrDataWordEnable),
|
|
.WR_DATA_VALID (1),
|
|
.RD_DATA_READY (1'b1),
|
|
.RST_IN (0),
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.CLK (CLK));
|
|
end
|
|
endgenerate
|
|
|
|
pipeline
|
|
#(// Parameters
|
|
.C_DEPTH (C_RX_OUTPUT_STAGES),
|
|
.C_WIDTH (`UPKT_RXR_MAXHDR_W + 2*(1 + C_OFFSET_WIDTH) +
|
|
`SIG_LBE_W + `SIG_FBE_W + `SIG_BARDECODE_W +
|
|
`SIG_TYPE_W),
|
|
.C_USE_MEMORY (0)
|
|
/*AUTOINSTPARAM*/)
|
|
output_pipeline
|
|
(// Outputs
|
|
.WR_DATA_READY (), // Pinned to 1
|
|
.RD_DATA ({wRxrHdr,wRxrBarDecoded,wRxrType,wRxrDataStartFlag,wRxrDataStartOffset,wRxrDataEndFlag,wRxrDataEndOffset,wRxrMetaLdwbe,wRxrMetaFdwbe}),
|
|
.RD_DATA_VALID (wRxrDataValid),
|
|
// Inputs
|
|
.WR_DATA ({wHdr,wBarDecoded,wType,wStartFlag,wStartOffset[C_OFFSET_WIDTH-1:0],wEndFlag,wEndOffset[C_OFFSET_WIDTH-1:0],wByteEnables}),
|
|
.WR_DATA_VALID (rValid),
|
|
.RD_DATA_READY (1'b1),
|
|
.RST_IN (rRST),
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.CLK (CLK));
|
|
|
|
endmodule
|
|
// Local Variables:
|
|
// verilog-library-directories:("." "../../../common/")
|
|
// End:
|