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580 lines
26 KiB
Verilog
580 lines
26 KiB
Verilog
// ----------------------------------------------------------------------
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// Copyright (c) 2016, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Filename: txr_engine_ultrascale.v
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// Version: 1.0
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// Verilog Standard: Verilog-2001
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// Description: The TXR Engine takes unformatted completions, formats
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// these packets into AXI-style packets. These packets must meet max-request,
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// max-payload, and payload termination requirements (see Read Completion
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// Boundary). The TXR Engine does not check these requirements during operation,
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// but may do so during simulation.
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//
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// This Engine is capable of operating at "line rate".
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//
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// Author: Dustin Richmond (@darichmond)
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//-----------------------------------------------------------------------------
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`include "trellis.vh"
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`include "ultrascale.vh"
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module txr_engine_ultrascale
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#(parameter C_PCI_DATA_WIDTH = 128,
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parameter C_PIPELINE_INPUT = 1,
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parameter C_PIPELINE_OUTPUT = 1,
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parameter C_DEPTH_PACKETS = 10,
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parameter C_MAX_PAYLOAD_DWORDS = 256)
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(// Interface: Clocks
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input CLK,
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// Interface: Resets
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input RST_BUS, // Replacement for generic RST_IN
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input RST_LOGIC, // Addition for RIFFA_RST
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output DONE_TXR_RST,
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// Interface: Configuration
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input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
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// Interface: RQ
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input S_AXIS_RQ_TREADY,
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output S_AXIS_RQ_TVALID,
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output S_AXIS_RQ_TLAST,
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output [C_PCI_DATA_WIDTH-1:0] S_AXIS_RQ_TDATA,
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output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_RQ_TKEEP,
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output [`SIG_RQ_TUSER_W-1:0] S_AXIS_RQ_TUSER,
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// Interface: TXR Engine
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input TXR_DATA_VALID,
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input [C_PCI_DATA_WIDTH-1:0] TXR_DATA,
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input TXR_DATA_START_FLAG,
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input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
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input TXR_DATA_END_FLAG,
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input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
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output TXR_DATA_READY,
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input TXR_META_VALID,
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input [`SIG_FBE_W-1:0] TXR_META_FDWBE,
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input [`SIG_LBE_W-1:0] TXR_META_LDWBE,
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input [`SIG_ADDR_W-1:0] TXR_META_ADDR,
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input [`SIG_LEN_W-1:0] TXR_META_LENGTH,
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input [`SIG_TAG_W-1:0] TXR_META_TAG,
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input [`SIG_TC_W-1:0] TXR_META_TC,
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input [`SIG_ATTR_W-1:0] TXR_META_ATTR,
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input [`SIG_TYPE_W-1:0] TXR_META_TYPE,
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input TXR_META_EP,
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output TXR_META_READY
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);
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localparam C_VENDOR = "XILINX";
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localparam C_DATA_WIDTH = C_PCI_DATA_WIDTH;
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localparam C_MAX_HDR_WIDTH = `UPKT_TXR_MAXHDR_W;
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localparam C_MAX_HDR_DWORDS = C_MAX_HDR_WIDTH/32;
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localparam C_MAX_ALIGN_DWORDS = 0;
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localparam C_MAX_NONPAY_DWORDS = C_MAX_HDR_DWORDS + C_MAX_ALIGN_DWORDS + 1;
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localparam C_MAX_PACKET_DWORDS = C_MAX_NONPAY_DWORDS + C_MAX_PAYLOAD_DWORDS;
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localparam C_PIPELINE_FORMATTER_INPUT = C_PIPELINE_INPUT;
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localparam C_PIPELINE_FORMATTER_OUTPUT = C_PIPELINE_OUTPUT;
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localparam C_FORMATTER_DELAY = C_PIPELINE_FORMATTER_OUTPUT + C_PIPELINE_FORMATTER_INPUT;
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localparam C_RST_COUNT = 10;
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/*AUTOWIRE*/
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/*AUTOINPUT*/
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///*AUTOOUTPUT*/
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wire wTxHdrReady;
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wire wTxHdrValid;
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wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
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wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
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wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
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wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
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wire wTxHdrNopayload;
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wire wTxDataReady;
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wire [C_PCI_DATA_WIDTH-1:0] wTxData;
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wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxDataEndOffset;
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wire wTxDataStartFlag;
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wire [(C_PCI_DATA_WIDTH/32)-1:0] wTxDataEndFlags;
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wire [(C_PCI_DATA_WIDTH/32)-1:0] wTxDataWordValid;
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wire [(C_PCI_DATA_WIDTH/32)-1:0] wTxDataWordReady;
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wire [C_PCI_DATA_WIDTH-1:0] wTxrPkt;
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wire wTxrPktEndFlag;
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wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxrPktEndOffset;
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wire wTxrPktStartFlag;
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wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxrPktStartOffset;
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wire wTxrPktValid;
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wire wTxrPktReady;
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wire wTransDoneRst;
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wire wTransRstOut;
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wire wDoneEngRst;
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wire wRst;
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wire [C_RST_COUNT:0] wShiftRegRst;
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assign DONE_TXR_RST = wTransDoneRst & wDoneEngRst;
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assign wRst = wShiftRegRst[C_RST_COUNT-3];
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assign wDoneEngRst = ~wShiftRegRst[C_RST_COUNT];
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shiftreg
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#(// Parameters
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.C_DEPTH (C_RST_COUNT),
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.C_WIDTH (1),
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.C_VALUE (1)
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/*AUTOINSTPARAM*/)
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rst_shiftreg
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(// Outputs
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.RD_DATA (wShiftRegRst),
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// Inputs
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.RST_IN (RST_BUS),
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.WR_DATA (wTransRstOut),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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txr_formatter_ultrascale
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#(.C_PIPELINE_OUTPUT (C_PIPELINE_FORMATTER_OUTPUT),
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.C_PIPELINE_INPUT (C_PIPELINE_FORMATTER_INPUT),
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/*AUTOINSTPARAM*/
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// Parameters
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.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
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.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
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.C_MAX_NONPAY_DWORDS (C_MAX_NONPAY_DWORDS),
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.C_MAX_PACKET_DWORDS (C_MAX_PACKET_DWORDS))
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txr_formatter_inst
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(// Outputs
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.TX_HDR_VALID (wTxHdrValid),
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.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
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.TX_HDR_NOPAYLOAD (wTxHdrNopayload),
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.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
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.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
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.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
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// Inputs
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.TX_HDR_READY (wTxHdrReady),
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.RST_IN (wRst),
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/*AUTOINST*/
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// Outputs
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.TXR_META_READY (TXR_META_READY),
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// Inputs
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.CLK (CLK),
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.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
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.TXR_META_VALID (TXR_META_VALID),
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.TXR_META_FDWBE (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
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.TXR_META_LDWBE (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
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.TXR_META_ADDR (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
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.TXR_META_LENGTH (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
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.TXR_META_TAG (TXR_META_TAG[`SIG_TAG_W-1:0]),
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.TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]),
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.TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
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.TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
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.TXR_META_EP (TXR_META_EP));
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tx_engine
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#(.C_DATA_WIDTH (C_PCI_DATA_WIDTH),
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/*AUTOINSTPARAM*/
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// Parameters
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.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
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.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
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.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
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.C_FORMATTER_DELAY (C_FORMATTER_DELAY),
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.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
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.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS),
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.C_VENDOR (C_VENDOR))
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txr_engine_inst
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(// Outputs
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.TX_HDR_READY (wTxHdrReady),
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.TX_DATA_READY (TXR_DATA_READY),
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.TX_PKT (wTxrPkt[C_DATA_WIDTH-1:0]),
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.TX_PKT_START_FLAG (wTxrPktStartFlag),
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.TX_PKT_START_OFFSET (wTxrPktStartOffset[clog2s(C_DATA_WIDTH/32)-1:0]),
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.TX_PKT_END_FLAG (wTxrPktEndFlag),
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.TX_PKT_END_OFFSET (wTxrPktEndOffset[clog2s(C_DATA_WIDTH/32)-1:0]),
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.TX_PKT_VALID (wTxrPktValid),
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// Inputs
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.TX_HDR_VALID (wTxHdrValid),
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.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
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.TX_HDR_NOPAYLOAD (wTxHdrNopayload),
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.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
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.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
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.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
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.TX_DATA_VALID (TXR_DATA_VALID),
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.TX_DATA (TXR_DATA[C_DATA_WIDTH-1:0]),
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.TX_DATA_START_FLAG (TXR_DATA_START_FLAG),
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.TX_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
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.TX_DATA_END_FLAG (TXR_DATA_END_FLAG),
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.TX_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
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.TX_PKT_READY (wTxrPktReady),
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.RST_IN (wRst),// TODO:
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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txr_translation_layer
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#(/*AUTOINSTPARAM*/
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// Parameters
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.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
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.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
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.C_RST_COUNT (C_RST_COUNT))
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txr_trans_inst
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(// Outputs
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.TXR_PKT_READY (wTxrPktReady),
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.DONE_RST (wTransDoneRst),
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.RST_OUT (wTransRstOut),
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// Inputs
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.TXR_PKT (wTxrPkt),
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.TXR_PKT_VALID (wTxrPktValid),
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.TXR_PKT_START_FLAG (wTxrPktStartFlag),
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.TXR_PKT_START_OFFSET (wTxrPktStartOffset),
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.TXR_PKT_END_FLAG (wTxrPktEndFlag),
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.TXR_PKT_END_OFFSET (wTxrPktEndOffset),
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/*AUTOINST*/
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// Outputs
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.S_AXIS_RQ_TVALID (S_AXIS_RQ_TVALID),
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.S_AXIS_RQ_TLAST (S_AXIS_RQ_TLAST),
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.S_AXIS_RQ_TDATA (S_AXIS_RQ_TDATA[C_PCI_DATA_WIDTH-1:0]),
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.S_AXIS_RQ_TKEEP (S_AXIS_RQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
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.S_AXIS_RQ_TUSER (S_AXIS_RQ_TUSER[`SIG_RQ_TUSER_W-1:0]),
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// Inputs
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.CLK (CLK),
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.RST_BUS (RST_BUS),
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.RST_LOGIC (RST_LOGIC),
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.S_AXIS_RQ_TREADY (S_AXIS_RQ_TREADY));
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endmodule // txr_engine_ultrascale
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module txr_formatter_ultrascale
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#(
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parameter C_PCI_DATA_WIDTH = 128,
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parameter C_PIPELINE_INPUT = 1,
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parameter C_PIPELINE_OUTPUT = 1,
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parameter C_MAX_HDR_WIDTH = `UPKT_TXR_MAXHDR_W,
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parameter C_MAX_NONPAY_DWORDS = 5,
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parameter C_MAX_PACKET_DWORDS = 10
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)
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(
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// Interface: Clocks
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input CLK,
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// Interface: Resets
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input RST_IN,
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// Interface: Configuration
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input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
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// Interface: TXR
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input TXR_META_VALID,
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input [`SIG_FBE_W-1:0] TXR_META_FDWBE,
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input [`SIG_LBE_W-1:0] TXR_META_LDWBE,
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input [`SIG_ADDR_W-1:0] TXR_META_ADDR,
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input [`SIG_LEN_W-1:0] TXR_META_LENGTH,
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input [`SIG_TAG_W-1:0] TXR_META_TAG,
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input [`SIG_TC_W-1:0] TXR_META_TC,
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input [`SIG_ATTR_W-1:0] TXR_META_ATTR,
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input [`SIG_TYPE_W-1:0] TXR_META_TYPE,
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input TXR_META_EP,
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output TXR_META_READY,
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// Interface: TX HDR
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output TX_HDR_VALID,
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output [C_MAX_HDR_WIDTH-1:0] TX_HDR,
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output [`SIG_LEN_W-1:0] TX_HDR_PAYLOAD_LEN,
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output [`SIG_NONPAY_W-1:0] TX_HDR_NONPAY_LEN,
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output [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,
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output TX_HDR_NOPAYLOAD,
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input TX_HDR_READY
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);
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wire wHdrNoPayload;
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wire [`UPKT_TXR_MAXHDR_W-1:0] wHdr;
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wire wTxHdrReady;
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wire wTxHdrValid;
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wire [`UPKT_TXR_MAXHDR_W-1:0] wTxHdr;
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wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
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wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
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wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
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wire wTxHdrNopayload;
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wire [`SIG_TYPE_W-1:0] wTxHdrType;
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// Generic Header Fields
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assign wHdr[`UPKT_TXR_ATYPE_R] = `UPKT_TXR_ATYPE_W'd0;
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assign wHdr[`UPKT_TXR_ADDR_R] = TXR_META_ADDR[63:2];
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assign wHdr[`UPKT_TXR_LENGTH_R] = {1'b0,TXR_META_LENGTH};
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assign wHdr[`UPKT_TXR_EP_R] = TXR_META_EP;
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`ifdef BE_HACK
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assign wHdr[`UPKT_TXR_FBE_R] = TXR_META_FDWBE;
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assign wHdr[`UPKT_TXR_LBE_R] = TXR_META_LDWBE;
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assign wHdr[`UPKT_TXR_RSVD0_R] = 0;
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`else
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assign wHdr[`UPKT_TXR_REQID_R] = CONFIG_COMPLETER_ID;
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`endif
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//assign wHdr[`UPKT_TXR_REQID_R] = `UPKT_TXR_REQID_W'd0;
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assign wHdr[`UPKT_TXR_TAG_R] = TXR_META_TAG;
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assign wHdr[`UPKT_TXR_CPLID_R] = `UPKT_TXR_CPLID_W'd0;
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assign wHdr[`UPKT_TXR_REQIDEN_R] = 0;
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assign wHdr[`UPKT_TXR_TC_R] = TXR_META_TC;
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assign wHdr[`UPKT_TXR_ATTR_R] = TXR_META_ATTR;
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assign wHdr[`UPKT_TXR_TD_R] = `UPKT_TXR_TD_W'd0;
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assign wTxHdr[`UPKT_TXR_TYPE_R] = trellis_to_upkt_type(wTxHdrType);
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assign wTxHdrNopayload = ~wTxHdrType[`TRLS_TYPE_PAY_I];
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assign wTxHdrNonpayLen = 4;
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assign wTxHdrPayloadLen = wTxHdrNopayload ? 0 : wTxHdr[`UPKT_TXR_LENGTH_R];
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assign wTxHdrPacketLen = wTxHdrNonpayLen + wTxHdrPayloadLen;
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pipeline
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#(
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// Parameters
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.C_DEPTH (C_PIPELINE_INPUT?1:0),
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.C_WIDTH (`UPKT_TXR_MAXHDR_W-1),
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.C_USE_MEMORY (0)
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/*AUTOINSTPARAM*/)
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input_inst
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(
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// Outputs
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.WR_DATA_READY (TXR_META_READY),
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.RD_DATA ({wTxHdr[`UPKT_TXR_MAXHDR_W-1:(`UPKT_TXR_TYPE_I + `UPKT_TXR_TYPE_W)],
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wTxHdr[`UPKT_TXR_TYPE_I-1:0],
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wTxHdrType}),
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.RD_DATA_VALID (wTxHdrValid),
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// Inputs
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.WR_DATA ({wHdr[`UPKT_TXR_MAXHDR_W-1:(`UPKT_TXR_TYPE_I + `UPKT_TXR_TYPE_W)],
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wHdr[`UPKT_TXR_TYPE_I-1:0],
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TXR_META_TYPE}),
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.WR_DATA_VALID (TXR_META_VALID),
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.RD_DATA_READY (wTxHdrReady),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN));
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pipeline
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#(
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// Parameters
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.C_DEPTH (C_PIPELINE_OUTPUT?1:0),
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.C_WIDTH (`UPKT_TXR_MAXHDR_W + 1 + `SIG_PACKETLEN_W + `SIG_LEN_W + `SIG_NONPAY_W),
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.C_USE_MEMORY (0)
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/*AUTOINSTPARAM*/)
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output_inst
|
|
(
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// Outputs
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.WR_DATA_READY (wTxHdrReady),
|
|
.RD_DATA ({TX_HDR,TX_HDR_NOPAYLOAD,TX_HDR_PACKET_LEN,TX_HDR_PAYLOAD_LEN,TX_HDR_NONPAY_LEN}),
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.RD_DATA_VALID (TX_HDR_VALID),
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// Inputs
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|
.WR_DATA ({wTxHdr,wTxHdrNopayload,wTxHdrPacketLen,wTxHdrPayloadLen,wTxHdrNonpayLen}),
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.WR_DATA_VALID (wTxHdrValid),
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.RD_DATA_READY (TX_HDR_READY),
|
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/*AUTOINST*/
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN));
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|
endmodule
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|
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module txr_translation_layer
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#(parameter C_PCI_DATA_WIDTH = 10'd128,
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parameter C_PIPELINE_INPUT = 1,
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parameter C_RST_COUNT = 1)
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(// Interface: Clocks
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input CLK,
|
|
|
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// Interface: Resets
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input RST_BUS, // Replacement for generic RST_IN
|
|
input RST_LOGIC, // Addition for RIFFA_RST
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|
output RST_OUT,
|
|
output DONE_RST,
|
|
|
|
// Interface: TXR Classic
|
|
output TXR_PKT_READY,
|
|
input [C_PCI_DATA_WIDTH-1:0] TXR_PKT,
|
|
input TXR_PKT_VALID,
|
|
input TXR_PKT_START_FLAG,
|
|
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_PKT_START_OFFSET,
|
|
input TXR_PKT_END_FLAG,
|
|
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_PKT_END_OFFSET,
|
|
|
|
// Interface: RQ
|
|
input S_AXIS_RQ_TREADY,
|
|
output S_AXIS_RQ_TVALID,
|
|
output S_AXIS_RQ_TLAST,
|
|
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_RQ_TDATA,
|
|
output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_RQ_TKEEP,
|
|
output [`SIG_RQ_TUSER_W-1:0] S_AXIS_RQ_TUSER);
|
|
|
|
localparam C_INPUT_STAGES = C_PIPELINE_INPUT != 0? 1:0;
|
|
localparam C_OUTPUT_STAGES = 1;
|
|
|
|
wire wTxrPktReady;
|
|
wire [C_PCI_DATA_WIDTH-1:0] wTxrPkt;
|
|
wire wTxrPktValid;
|
|
wire wTxrPktStartFlag;
|
|
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxrPktStartOffset;
|
|
wire wTxrPktEndFlag;
|
|
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxrPktEndOffset;
|
|
|
|
wire wSAxisRqTReady;
|
|
wire wSAxisRqTValid;
|
|
wire wSAxisRqTLast;
|
|
wire [C_PCI_DATA_WIDTH-1:0] wSAxisRqTData;
|
|
wire [(C_PCI_DATA_WIDTH/32)-1:0] wSAxisRqTKeep;
|
|
wire [`SIG_RQ_TUSER_W-1:0] wSAxisRqTUser;
|
|
|
|
wire _wSAxisRqTReady;
|
|
wire _wSAxisRqTValid;
|
|
wire _wSAxisRqTLast;
|
|
wire [C_PCI_DATA_WIDTH-1:0] _wSAxisRqTData;
|
|
wire [(C_PCI_DATA_WIDTH/32)-1:0] _wSAxisRqTKeep;
|
|
|
|
wire wRst;
|
|
wire wRstWaiting;
|
|
|
|
/*ASSIGN TXR -> RQ*/
|
|
assign wTxrPktReady = _wSAxisRqTReady;
|
|
assign _wSAxisRqTValid = wTxrPktValid;
|
|
assign _wSAxisRqTLast = wTxrPktEndFlag;
|
|
assign _wSAxisRqTData = wTxrPkt;
|
|
|
|
// BE Hack
|
|
assign wSAxisRqTUser[3:0] = wTxrPkt[(`UPKT_TXR_FBE_I % C_PCI_DATA_WIDTH) +: `UPKT_TXR_FBE_W];
|
|
assign wSAxisRqTUser[7:4] = wTxrPkt[(`UPKT_TXR_LBE_I % C_PCI_DATA_WIDTH) +: `UPKT_TXR_LBE_W];
|
|
assign wSAxisRqTUser[`SIG_RQ_TUSER_W-1:8] = 0;
|
|
assign RST_OUT = wRst;
|
|
// This reset controller assumes there is always an output stage
|
|
reset_controller
|
|
#(/*AUTOINSTPARAM*/
|
|
// Parameters
|
|
.C_RST_COUNT (C_RST_COUNT))
|
|
rc
|
|
(// Outputs
|
|
.RST_OUT (wRst),
|
|
.WAITING_RESET (wRstWaiting),
|
|
// Inputs
|
|
.RST_IN (RST_BUS),
|
|
.SIGNAL_RST (RST_LOGIC),
|
|
.WAIT_RST (S_AXIS_RQ_TVALID),
|
|
.NEXT_CYC_RST (S_AXIS_RQ_TREADY & S_AXIS_RQ_TLAST),
|
|
/*AUTOINST*/
|
|
// Outputs
|
|
.DONE_RST (DONE_RST),
|
|
// Inputs
|
|
.CLK (CLK));
|
|
|
|
|
|
pipeline
|
|
#(// Parameters
|
|
.C_DEPTH (C_INPUT_STAGES),
|
|
.C_WIDTH (C_PCI_DATA_WIDTH + 2*(1+clog2s(C_PCI_DATA_WIDTH/32))),
|
|
.C_USE_MEMORY (0)
|
|
/*AUTOINSTPARAM*/)
|
|
input_inst
|
|
(
|
|
// Outputs
|
|
.WR_DATA_READY (TXR_PKT_READY),
|
|
.RD_DATA ({wTxrPkt,wTxrPktStartFlag,wTxrPktStartOffset,wTxrPktEndFlag,wTxrPktEndOffset}),
|
|
.RD_DATA_VALID (wTxrPktValid),
|
|
// Inputs
|
|
.WR_DATA ({TXR_PKT,TXR_PKT_START_FLAG,TXR_PKT_START_OFFSET,
|
|
TXR_PKT_END_FLAG,TXR_PKT_END_OFFSET}),
|
|
.WR_DATA_VALID (TXR_PKT_VALID),
|
|
.RD_DATA_READY (wTxrPktReady),
|
|
.RST_IN (wRst),
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.CLK (CLK));
|
|
|
|
|
|
offset_to_mask
|
|
#(
|
|
// Parameters
|
|
.C_MASK_SWAP (0),
|
|
.C_MASK_WIDTH (C_PCI_DATA_WIDTH/32)
|
|
/*AUTOINSTPARAM*/)
|
|
otom_inst
|
|
(
|
|
// Outputs
|
|
.MASK (_wSAxisRqTKeep),
|
|
// Inputs
|
|
.OFFSET_ENABLE (wTxrPktEndFlag),
|
|
.OFFSET (wTxrPktEndOffset)
|
|
/*AUTOINST*/);
|
|
|
|
|
|
pipeline
|
|
#(
|
|
// Parameters
|
|
.C_DEPTH (64/C_PCI_DATA_WIDTH),
|
|
.C_WIDTH (C_PCI_DATA_WIDTH + 1 + (C_PCI_DATA_WIDTH/32)),
|
|
.C_USE_MEMORY (0)
|
|
/*AUTOINSTPARAM*/)
|
|
fbe_hack_inst
|
|
(
|
|
// Outputs
|
|
.WR_DATA_READY (_wSAxisRqTReady),
|
|
.RD_DATA ({wSAxisRqTData,wSAxisRqTLast,wSAxisRqTKeep}),
|
|
.RD_DATA_VALID (wSAxisRqTValid),
|
|
// Inputs
|
|
.WR_DATA ({_wSAxisRqTData,_wSAxisRqTLast,_wSAxisRqTKeep}),
|
|
.WR_DATA_VALID (_wSAxisRqTValid),
|
|
.RD_DATA_READY (wSAxisRqTReady),
|
|
.RST_IN (wRst),
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.CLK (CLK));
|
|
|
|
pipeline
|
|
#(
|
|
// Parameters
|
|
.C_DEPTH (C_OUTPUT_STAGES),
|
|
.C_WIDTH (C_PCI_DATA_WIDTH + 1 + (C_PCI_DATA_WIDTH/32) + `SIG_RQ_TUSER_W),
|
|
.C_USE_MEMORY (0)
|
|
/*AUTOINSTPARAM*/)
|
|
output_inst
|
|
(
|
|
// Outputs
|
|
.WR_DATA_READY (wSAxisRqTReady),
|
|
.RD_DATA ({S_AXIS_RQ_TDATA,S_AXIS_RQ_TLAST,S_AXIS_RQ_TKEEP,S_AXIS_RQ_TUSER}),
|
|
.RD_DATA_VALID (S_AXIS_RQ_TVALID),
|
|
// Inputs
|
|
.WR_DATA ({wSAxisRqTData,wSAxisRqTLast,wSAxisRqTKeep,wSAxisRqTUser}),
|
|
.WR_DATA_VALID (wSAxisRqTValid & ~wRstWaiting),
|
|
.RD_DATA_READY (S_AXIS_RQ_TREADY),
|
|
.RST_IN (wRst),
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.CLK (CLK));
|
|
|
|
endmodule
|
|
// Local Variables:
|
|
// verilog-library-directories:("." "../../../common/" "../../common/")
|
|
// End:
|