mirror of
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478 lines
23 KiB
Verilog
478 lines
23 KiB
Verilog
// ----------------------------------------------------------------------
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// Copyright (c) 2015, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Filename: rxr_engine_128.v
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// Version: 1.0
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// Verilog Standard: Verilog-2001
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// Description: The RXR Engine (Classic) takes a single stream of TLP
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// packets and provides the request packets on the RXR Interface.
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// This Engine is capable of operating at "line rate".
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// Author: Dustin Richmond (@darichmond)
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//-----------------------------------------------------------------------------
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`include "trellis.vh"
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`include "tlp.vh"
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module rxr_engine_128
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#(parameter C_PCI_DATA_WIDTH = 128,
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parameter C_RX_PIPELINE_DEPTH=10)
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(// Interface: Clocks
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input CLK,
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// Interface: Resets
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input RST_BUS, // Replacement for generic RST_IN
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input RST_LOGIC, // Addition for RIFFA_RST
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output DONE_RXR_RST,
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// Interface: RX Classic
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input [C_PCI_DATA_WIDTH-1:0] RX_TLP,
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input RX_TLP_VALID,
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input RX_TLP_START_FLAG,
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input [`SIG_OFFSET_W-1:0] RX_TLP_START_OFFSET,
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input RX_TLP_END_FLAG,
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input [`SIG_OFFSET_W-1:0] RX_TLP_END_OFFSET,
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input [`SIG_BARDECODE_W-1:0] RX_TLP_BAR_DECODE,
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// Interface: RXR
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output [C_PCI_DATA_WIDTH-1:0] RXR_DATA,
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output RXR_DATA_VALID,
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output [(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_WORD_ENABLE,
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output RXR_DATA_START_FLAG,
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output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET,
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output RXR_DATA_END_FLAG,
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output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET,
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output [`SIG_FBE_W-1:0] RXR_META_FDWBE,
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output [`SIG_LBE_W-1:0] RXR_META_LDWBE,
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output [`SIG_TC_W-1:0] RXR_META_TC,
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output [`SIG_ATTR_W-1:0] RXR_META_ATTR,
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output [`SIG_TAG_W-1:0] RXR_META_TAG,
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output [`SIG_TYPE_W-1:0] RXR_META_TYPE,
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output [`SIG_ADDR_W-1:0] RXR_META_ADDR,
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output [`SIG_BARDECODE_W-1:0] RXR_META_BAR_DECODED,
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output [`SIG_REQID_W-1:0] RXR_META_REQUESTER_ID,
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output [`SIG_LEN_W-1:0] RXR_META_LENGTH,
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output RXR_META_EP,
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// Interface: RX Shift Register
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input [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] RX_SR_DATA,
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input [C_RX_PIPELINE_DEPTH:0] RX_SR_EOP,
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input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0] RX_SR_END_OFFSET,
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input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0] RX_SR_START_OFFSET,
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input [C_RX_PIPELINE_DEPTH:0] RX_SR_SOP,
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input [C_RX_PIPELINE_DEPTH:0] RX_SR_VALID
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);
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/*AUTOWIRE*/
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///*AUTOOUTPUT*/
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// End of automatics
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localparam C_RX_BE_W = (`SIG_FBE_W+`SIG_LBE_W);
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localparam C_RX_INPUT_STAGES = 1;
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localparam C_RX_OUTPUT_STAGES = 1;
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localparam C_RX_COMPUTATION_STAGES = 1;
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localparam C_RX_HDR_STAGES = 1; // Specific to the Xilinx 128-bit RXR Engine
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localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES + C_RX_HDR_STAGES;
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localparam C_OFFSET_WIDTH = clog2s(C_PCI_DATA_WIDTH/32);
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localparam C_STRADDLE_W = 64;
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localparam C_HDR_NOSTRADDLE_I = C_RX_INPUT_STAGES * C_PCI_DATA_WIDTH;
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localparam C_OUTPUT_STAGE_WIDTH = (C_PCI_DATA_WIDTH/32) + 2 + clog2s(C_PCI_DATA_WIDTH/32) + 1 + `SIG_FBE_W + `SIG_LBE_W + `SIG_TC_W + `SIG_ATTR_W + `SIG_TAG_W + `SIG_TYPE_W + `SIG_ADDR_W + `SIG_BARDECODE_W + `SIG_REQID_W + `SIG_LEN_W;
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// Header Reg Inputs
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wire [`SIG_OFFSET_W-1:0] __wRxrStartOffset;
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wire [`SIG_OFFSET_W-1:0] __wRxrStraddledStartOffset;
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wire [`TLP_MAXHDR_W-1:0] __wRxrHdr;
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wire [`TLP_MAXHDR_W-1:0] __wRxrHdrStraddled;
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wire [`TLP_MAXHDR_W-1:0] __wRxrHdrNotStraddled;
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wire __wRxrHdrValid;
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wire [`TLP_TYPE_W-1:0] __wRxrHdrType;
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wire [`TLP_TYPE_W-1:0] __wRxrHdrTypeStraddled;
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wire __wRxrHdrSOP; // Asserted on non-straddle SOP
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wire __wRxrHdrSOPStraddle;
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wire __wRxrHdr4DWHWDataSF;
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// Header Reg Outputs
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wire _wRxrHdrValid;
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wire [`TLP_MAXHDR_W-1:0] _wRxrHdr;
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wire [`SIG_ADDR_W-1:0] _wRxrAddrUnformatted;
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wire [`SIG_ADDR_W-1:0] _wRxrAddr;
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wire [63:0] _wRxrTlpMetadata;
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wire [`TLP_TYPE_W-1:0] _wRxrType;
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wire [`TLP_LEN_W-1:0] _wRxrLength;
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wire [2:0] _wRxrHdrHdrLen;// TODO:
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wire [`SIG_OFFSET_W-1:0] _wRxrHdrStartOffset;// TODO:
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wire _wRxrHdrDelayedSOP;
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wire _wRxrHdrSOPStraddle;
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wire _wRxrHdrSOP;
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wire _wRxrHdrSF;
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wire _wRxrHdrEF;
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wire _wRxrHdrSCP; // Single Cycle Packet
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wire _wRxrHdrMCP; // Multi Cycle Packet
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wire _wRxrHdrRegSF;
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wire _wRxrHdrRegValid;
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wire _wRxrHdr4DWHSF;
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wire _wRxrHdr4DWHNoDataSF;
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wire _wRxrHdr4DWHWDataSF;
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wire _wRxrHdr3DWHSF;
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wire [2:0] _wRxrHdrDataSoff;
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wire [1:0] _wRxrHdrDataEoff;
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wire [3:0] _wRxrHdrStartMask;
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wire [3:0] _wRxrHdrEndMask;
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// Header Reg Outputs
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wire wRxrHdrSF;
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wire wRxrHdrEF;
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wire wRxrHdrValid;
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wire [`TLP_MAXHDR_W-1:0] wRxrHdr;
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wire [63:0] wRxrMetadata;
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wire [`TLP_TYPE_W-1:0] wRxrType;
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wire [`TLP_LEN_W-1:0] wRxrLength;
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wire [2:0] wRxrHdrLength; // TODO:
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wire [`SIG_OFFSET_W-1:0] wRxrHdrStartOffset; // TODO:
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wire wRxrHdrSCP; // Single Cycle Packet
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wire wRxrHdrMCP; // Multi Cycle Packet
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wire [1:0] wRxrHdrDataSoff;
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wire [3:0] wRxrHdrStartMask;
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wire [3:0] wRxrHdrEndMask;
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// Output Register Inputs
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wire [C_PCI_DATA_WIDTH-1:0] wRxrData;
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wire wRxrDataValid;
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wire [(C_PCI_DATA_WIDTH/32)-1:0] wRxrDataWordEnable;
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wire wRxrDataStartFlag;
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wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wRxrDataStartOffset;
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wire wRxrDataEndFlag;
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wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wRxrDataEndOffset;
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wire [`SIG_FBE_W-1:0] wRxrMetaFdwbe;
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wire [`SIG_LBE_W-1:0] wRxrMetaLdwbe;
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wire [`SIG_TC_W-1:0] wRxrMetaTC;
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wire [`SIG_ATTR_W-1:0] wRxrMetaAttr;
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wire [`SIG_TAG_W-1:0] wRxrMetaTag;
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wire [`SIG_TYPE_W-1:0] wRxrMetaType;
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wire [`SIG_ADDR_W-1:0] wRxrMetaAddr;
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wire [`SIG_BARDECODE_W-1:0] wRxrMetaBarDecoded;
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wire [`SIG_REQID_W-1:0] wRxrMetaRequesterId;
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wire [`SIG_LEN_W-1:0] wRxrMetaLength;
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wire wRxrMetaEP;
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reg rStraddledSOP;
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reg rStraddledSOPSplit;
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reg rRST;
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assign DONE_RXR_RST = ~rRST;
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// ----- Header Register -----
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assign __wRxrHdrSOP = RX_SR_SOP[C_RX_INPUT_STAGES] & ~__wRxrStartOffset[1];
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assign __wRxrHdrSOPStraddle = RX_SR_SOP[C_RX_INPUT_STAGES] & __wRxrStraddledStartOffset[1];
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assign __wRxrHdrNotStraddled = RX_SR_DATA[C_HDR_NOSTRADDLE_I +: C_PCI_DATA_WIDTH];
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assign __wRxrHdrStraddled = {RX_SR_DATA[C_RX_INPUT_STAGES*C_PCI_DATA_WIDTH +: C_STRADDLE_W],
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RX_SR_DATA[(C_RX_INPUT_STAGES+1)*C_PCI_DATA_WIDTH + C_STRADDLE_W +: C_STRADDLE_W ]};
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assign __wRxrStartOffset = RX_SR_START_OFFSET[`SIG_OFFSET_W*C_RX_INPUT_STAGES +: `SIG_OFFSET_W];
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assign __wRxrStraddledStartOffset = RX_SR_START_OFFSET[`SIG_OFFSET_W*(C_RX_INPUT_STAGES) +: `SIG_OFFSET_W];
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assign __wRxrHdrValid = __wRxrHdrSOP | ((rStraddledSOP | rStraddledSOPSplit) & RX_SR_VALID[C_RX_INPUT_STAGES]);
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assign __wRxrHdr4DWHWDataSF = (_wRxrHdr[`TLP_4DWHBIT_I] & _wRxrHdr[`TLP_PAYBIT_I] & RX_SR_VALID[C_RX_INPUT_STAGES] & _wRxrHdrDelayedSOP);
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assign _wRxrHdrHdrLen = {_wRxrHdr[`TLP_4DWHBIT_I],~_wRxrHdr[`TLP_4DWHBIT_I],~_wRxrHdr[`TLP_4DWHBIT_I]};
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assign _wRxrHdrDataSoff = {1'b0,_wRxrHdrSOPStraddle,1'b0} + _wRxrHdrHdrLen;
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assign _wRxrHdrRegSF = RX_SR_SOP[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
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assign _wRxrHdrRegValid = RX_SR_VALID[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
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assign _wRxrHdr4DWHNoDataSF = _wRxrHdr[`TLP_4DWHBIT_I] & ~_wRxrHdr[`TLP_PAYBIT_I] & _wRxrHdrSOP;
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assign _wRxrHdr4DWHSF = _wRxrHdr4DWHNoDataSF | (_wRxrHdr4DWHWDataSF & _wRxrHdrRegValid);
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assign _wRxrHdr3DWHSF = ~_wRxrHdr[`TLP_4DWHBIT_I] & _wRxrHdrSOP;
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assign _wRxrHdrSF = (_wRxrHdr3DWHSF | _wRxrHdr4DWHSF | _wRxrHdrSOPStraddle);
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assign _wRxrHdrEF = RX_SR_EOP[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
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assign _wRxrHdrDataEoff = RX_SR_END_OFFSET[(C_RX_INPUT_STAGES+C_RX_HDR_STAGES)*`SIG_OFFSET_W +: C_OFFSET_WIDTH];
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assign _wRxrHdrSCP = _wRxrHdrSF & _wRxrHdrEF & (_wRxrHdr[`TLP_TYPE_R] == `TLP_TYPE_REQ);
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assign _wRxrHdrMCP = (_wRxrHdrSF & ~_wRxrHdrEF & (_wRxrHdr[`TLP_TYPE_R] == `TLP_TYPE_REQ)) |
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(wRxrHdrMCP & ~wRxrHdrEF);
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assign _wRxrHdrStartMask = {4{_wRxrHdr[`TLP_PAYBIT_I]}} << (_wRxrHdrSF ? _wRxrHdrDataSoff[1:0] : 0);
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assign wRxrDataWordEnable = wRxrHdrEndMask & wRxrHdrStartMask & {4{wRxrDataValid}};
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assign wRxrDataValid = wRxrHdrSCP | wRxrHdrMCP;
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assign wRxrDataStartFlag = wRxrHdrSF;
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assign wRxrDataEndFlag = wRxrHdrEF;
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assign wRxrDataStartOffset = wRxrHdrDataSoff;
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assign wRxrMetaFdwbe = wRxrHdr[`TLP_REQFBE_R];
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assign wRxrMetaLdwbe = wRxrHdr[`TLP_REQLBE_R];
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assign wRxrMetaTC = wRxrHdr[`TLP_TC_R];
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assign wRxrMetaAttr = {wRxrHdr[`TLP_ATTR1_R], wRxrHdr[`TLP_ATTR0_R]};
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assign wRxrMetaTag = wRxrHdr[`TLP_REQTAG_R];
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assign wRxrMetaAddr = wRxrHdr[`TLP_REQADDRDW0_I +: `TLP_REQADDR_W];/* TODO: REQADDR_R*/
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assign wRxrMetaRequesterId = wRxrHdr[`TLP_REQREQID_R];
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assign wRxrMetaLength = wRxrHdr[`TLP_LEN_R];
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assign wRxrMetaEP = wRxrHdr[`TLP_EP_R];
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assign wRxrMetaType = tlp_to_trellis_type({wRxrHdr[`TLP_FMT_R],wRxrHdr[`TLP_TYPE_R]});
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assign RXR_DATA = RX_SR_DATA[C_PCI_DATA_WIDTH*C_TOTAL_STAGES +: C_PCI_DATA_WIDTH];
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assign RXR_DATA_END_OFFSET = RX_SR_END_OFFSET[`SIG_OFFSET_W*(C_TOTAL_STAGES) +: C_OFFSET_WIDTH];
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always @(posedge CLK) begin
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rStraddledSOP <= __wRxrHdrSOPStraddle;
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// Set Straddled SOP Split when there is a straddled packet where the
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// header is not contiguous. (Not sure if this is ever possible, but
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// better safe than sorry assert Straddled SOP Split. See Virtex 6 PCIe
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// errata.
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if(__wRxrHdrSOP | rRST) begin
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rStraddledSOPSplit <=0;
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end else begin
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rStraddledSOPSplit <= (__wRxrHdrSOPStraddle | rStraddledSOPSplit) & ~RX_SR_VALID[C_RX_INPUT_STAGES];
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end
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end
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always @(posedge CLK) begin
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rRST <= RST_BUS | RST_LOGIC;
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end
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mux
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#(
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// Parameters
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.C_NUM_INPUTS (2),
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.C_CLOG_NUM_INPUTS (1),
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.C_WIDTH (`TLP_MAXHDR_W),
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.C_MUX_TYPE ("SELECT")
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/*AUTOINSTPARAM*/)
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hdr_mux
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(
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// Outputs
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.MUX_OUTPUT (__wRxrHdr[`TLP_MAXHDR_W-1:0]),
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// Inputs
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.MUX_INPUTS ({__wRxrHdrStraddled[`TLP_MAXHDR_W-1:0],
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__wRxrHdrNotStraddled[`TLP_MAXHDR_W-1:0]}),
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.MUX_SELECT (rStraddledSOP | rStraddledSOPSplit)
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/*AUTOINST*/);
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register
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#(
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// Parameters
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.C_WIDTH (64 + 1),
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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hdr_register_63_0
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(
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// Outputs
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.RD_DATA ({_wRxrHdr[C_STRADDLE_W-1:0], _wRxrHdrValid}),
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// Inputs
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.WR_DATA ({__wRxrHdr[C_STRADDLE_W-1:0], __wRxrHdrValid}),
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.WR_EN (__wRxrHdrSOP | rStraddledSOP),
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.RST_IN (0),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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register
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#(
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// Parameters
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.C_WIDTH (3),
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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sf4dwh
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(
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// Outputs
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.RD_DATA ({_wRxrHdr4DWHWDataSF, _wRxrHdrSOPStraddle,_wRxrHdrSOP}),
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// Inputs
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.WR_DATA ({__wRxrHdr4DWHWDataSF,rStraddledSOP,__wRxrHdrSOP}),
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.WR_EN (1),
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.RST_IN (0),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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register
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#(
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// Parameters
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.C_WIDTH (1),
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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delayed_sop
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(
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// Outputs
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.RD_DATA ({_wRxrHdrDelayedSOP}),
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// Inputs
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.WR_DATA ({__wRxrHdrSOP}),
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.WR_EN (RX_SR_VALID[C_RX_INPUT_STAGES]),
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.RST_IN (0),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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register
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#(
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// Parameters
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.C_WIDTH (64),
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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hdr_register_127_64
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(
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// Outputs
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.RD_DATA (_wRxrHdr[`TLP_MAXHDR_W-1:C_STRADDLE_W]),
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// Inputs
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.WR_DATA (__wRxrHdr[`TLP_MAXHDR_W-1:C_STRADDLE_W]),
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.WR_EN (__wRxrHdrSOP | rStraddledSOP | rStraddledSOPSplit), // Non straddled start, Straddled, or straddled split
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.RST_IN (0),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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// ----- Computation Register -----
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register
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#(
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// Parameters
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.C_WIDTH (64 + 4),/* TODO: TLP_METADATA_W*/
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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metadata
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(// Outputs
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.RD_DATA ({wRxrHdr[`TLP_REQMETADW0_I +: 64],
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wRxrHdrSF,wRxrHdrDataSoff,
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wRxrHdrEF}),/* TODO: TLP_METADATA_R and other signals*/
|
|
// Inputs
|
|
.RST_IN (0),
|
|
.WR_DATA ({_wRxrHdr[`TLP_REQMETADW0_I +: 64],
|
|
_wRxrHdrSF,_wRxrHdrDataSoff[1:0],
|
|
_wRxrHdrEF}),/* TODO: TLP_METADATA_R*/
|
|
.WR_EN (1),
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.CLK (CLK));
|
|
|
|
register
|
|
#(// Parameters
|
|
.C_WIDTH (3+8),
|
|
.C_VALUE (0)
|
|
/*AUTOINSTPARAM*/)
|
|
metadata_valid
|
|
(// Output
|
|
.RD_DATA ({wRxrHdrValid,
|
|
wRxrHdrSCP, wRxrHdrMCP,
|
|
wRxrHdrEndMask, wRxrHdrStartMask}),
|
|
// Inputs
|
|
.RST_IN (0),
|
|
.WR_DATA ({_wRxrHdrValid,
|
|
_wRxrHdrSCP, _wRxrHdrMCP,
|
|
_wRxrHdrEndMask, _wRxrHdrStartMask}),
|
|
.WR_EN (1),
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.CLK (CLK));
|
|
|
|
register
|
|
#(// Parameters
|
|
.C_WIDTH (`SIG_ADDR_W/2),
|
|
.C_VALUE (0)
|
|
/*AUTOINSTPARAM*/)
|
|
addr_63_32
|
|
(// Outputs
|
|
.RD_DATA (wRxrHdr[`TLP_REQADDRHI_R]),
|
|
// Inputs
|
|
.RST_IN (~_wRxrHdr[`TLP_4DWHBIT_I]),
|
|
.WR_DATA (_wRxrHdr[`TLP_REQADDRLO_R]), // Instead of a mux, we'll use the reset
|
|
.WR_EN (1),
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.CLK (CLK));
|
|
|
|
register
|
|
#(// Parameters
|
|
.C_WIDTH (`SIG_ADDR_W/2),
|
|
.C_VALUE (0)
|
|
/*AUTOINSTPARAM*/)
|
|
addr_31_0
|
|
(// Outputs
|
|
.RD_DATA (wRxrHdr[`TLP_REQADDRLO_R]),
|
|
// Inputs
|
|
.RST_IN (0),// Never need to reset
|
|
.WR_DATA (_wRxrHdr[`TLP_4DWHBIT_I] ? _wRxrHdr[`TLP_REQADDRHI_R] : _wRxrHdr[`TLP_REQADDRLO_R]),
|
|
.WR_EN (1),
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.CLK (CLK));
|
|
|
|
offset_to_mask
|
|
#(// Parameters
|
|
.C_MASK_SWAP (0),
|
|
.C_MASK_WIDTH (4)
|
|
/*AUTOINSTPARAM*/)
|
|
o2m_ef
|
|
(// Outputs
|
|
.MASK (_wRxrHdrEndMask),
|
|
// Inputs
|
|
.OFFSET_ENABLE (_wRxrHdrEF),
|
|
.OFFSET (_wRxrHdrDataEoff)
|
|
/*AUTOINST*/);
|
|
|
|
pipeline
|
|
#(// Parameters
|
|
.C_DEPTH (C_RX_OUTPUT_STAGES),
|
|
.C_WIDTH (C_OUTPUT_STAGE_WIDTH),// TODO:
|
|
.C_USE_MEMORY (0)
|
|
/*AUTOINSTPARAM*/)
|
|
output_pipeline
|
|
(// Outputs
|
|
.WR_DATA_READY (), // Pinned to 1
|
|
.RD_DATA ({RXR_DATA_WORD_ENABLE, RXR_DATA_START_FLAG, RXR_DATA_START_OFFSET,
|
|
RXR_DATA_END_FLAG,
|
|
RXR_META_FDWBE, RXR_META_LDWBE, RXR_META_TC,
|
|
RXR_META_ATTR, RXR_META_TAG, RXR_META_TYPE,
|
|
RXR_META_ADDR, RXR_META_BAR_DECODED, RXR_META_REQUESTER_ID,
|
|
RXR_META_LENGTH, RXR_META_EP}),
|
|
.RD_DATA_VALID (RXR_DATA_VALID),
|
|
// Inputs
|
|
.WR_DATA ({wRxrDataWordEnable, wRxrDataStartFlag, wRxrDataStartOffset,
|
|
wRxrDataEndFlag,
|
|
wRxrMetaFdwbe, wRxrMetaLdwbe, wRxrMetaTC,
|
|
wRxrMetaAttr, wRxrMetaTag, wRxrMetaType,
|
|
wRxrMetaAddr, wRxrMetaBarDecoded, wRxrMetaRequesterId,
|
|
wRxrMetaLength, wRxrMetaEP}),
|
|
.WR_DATA_VALID (wRxrDataValid),
|
|
.RD_DATA_READY (1'b1),
|
|
.RST_IN (rRST),
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.CLK (CLK));
|
|
endmodule
|
|
// Local Variables:
|
|
// verilog-library-directories:("." "../../../common")
|
|
// End:
|