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dc93333b9c
The error occured when calculating the actual header fifo depth, C_ACTUAL_FIFO_DEPTH. This was initially clog2(C_FIFO_DEPTH), but should have been 1<<clog2(C_FIFO_DEPTH).
158 lines
7.2 KiB
Verilog
158 lines
7.2 KiB
Verilog
// ----------------------------------------------------------------------
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// Copyright (c) 2015, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Filename: tx_data_pipeline
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// Version: 1.0
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// Verilog Standard: Verilog-2001
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//
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// Description: The TX Data pipeline module takes arbitrarily 32-bit aligned data
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// from the WR_TX_DATA interface and shifts the data so that it is 0-bit
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// aligned. This data is presented on a set of N fifos, where N =
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// (C_DATA_WIDTH/32). Each fifo provides it's own VALID signal and is
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// controlled by a READY signal. Each fifo also provides an independent DATA bus
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// and additional END_FLAG signal which inidicates that the dword provided in this
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// fifo is the last dword in the current payload. The START_FLAG signal indicates
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// that the dword at index N = 0 is the start of a new packet.
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//
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// The TX Data Pipeline is built from two modules: tx_data_shift.v and
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// tx_data_fifo.v. See these modules for more information.
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//
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// Author: Dustin Richmond (@darichmond)
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//----------------------------------------------------------------------------
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`include "trellis.vh" // Defines the user-facing signal widths.
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module tx_data_pipeline
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#(parameter C_DATA_WIDTH = 128,
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parameter C_PIPELINE_INPUT = 1,
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parameter C_PIPELINE_OUTPUT = 1,
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parameter C_MAX_PAYLOAD_DWORDS = 256,
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parameter C_DEPTH_PACKETS = 10,
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parameter C_VENDOR = "ALTERA")
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(// Interface: Clocks
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input CLK,
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// Interface: Resets
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input RST_IN,
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// Interface: WR TX DATA
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input WR_TX_DATA_VALID,
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input [C_DATA_WIDTH-1:0] WR_TX_DATA,
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input WR_TX_DATA_START_FLAG,
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input [clog2s(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_START_OFFSET,
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input WR_TX_DATA_END_FLAG,
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input [clog2s(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_END_OFFSET,
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output WR_TX_DATA_READY,
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// Interface: TX DATA FIFOS
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input [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_WORD_READY,
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output [C_DATA_WIDTH-1:0] RD_TX_DATA,
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output [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_END_FLAGS,
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output RD_TX_DATA_START_FLAG,
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output [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_WORD_VALID,
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output RD_TX_DATA_PACKET_VALID);
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wire wRdTxDataValid;
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wire wRdTxDataReady;
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wire wRdTxDataStartFlag;
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wire [C_DATA_WIDTH-1:0] wRdTxData;
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wire [(C_DATA_WIDTH/32)-1:0] wRdTxDataEndFlags;
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wire [(C_DATA_WIDTH/32)-1:0] wRdTxDataWordValid;
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/*AUTOWIRE*/
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/*AUTOINPUT*/
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/*AUTOOUTPUT*/
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tx_data_shift
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#(.C_PIPELINE_OUTPUT (0),
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/*AUTOINSTPARAM*/
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// Parameters
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.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
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.C_DATA_WIDTH (C_DATA_WIDTH),
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.C_VENDOR (C_VENDOR))
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tx_shift_inst
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(// Outputs
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.RD_TX_DATA (wRdTxData),
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.RD_TX_DATA_VALID (wRdTxDataValid),
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.RD_TX_DATA_START_FLAG (wRdTxDataStartFlag),
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.RD_TX_DATA_WORD_VALID (wRdTxDataWordValid),
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.RD_TX_DATA_END_FLAGS (wRdTxDataEndFlags),
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// Inputs
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.RD_TX_DATA_READY (wRdTxDataReady),
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/*AUTOINST*/
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// Outputs
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.WR_TX_DATA_READY (WR_TX_DATA_READY),
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN),
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.WR_TX_DATA_VALID (WR_TX_DATA_VALID),
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.WR_TX_DATA (WR_TX_DATA[C_DATA_WIDTH-1:0]),
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.WR_TX_DATA_START_FLAG (WR_TX_DATA_START_FLAG),
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.WR_TX_DATA_START_OFFSET (WR_TX_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
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.WR_TX_DATA_END_FLAG (WR_TX_DATA_END_FLAG),
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.WR_TX_DATA_END_OFFSET (WR_TX_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]));
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// TX Data Fifo
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tx_data_fifo
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#(// Parameters
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.C_PIPELINE_INPUT (1),
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/*AUTOINSTPARAM*/
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// Parameters
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.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
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.C_DATA_WIDTH (C_DATA_WIDTH),
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.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS))
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txdf_inst
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(// Outputs
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.WR_TX_DATA_READY (wRdTxDataReady),
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.RD_TX_DATA (RD_TX_DATA[C_DATA_WIDTH-1:0]),
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.RD_TX_DATA_START_FLAG (RD_TX_DATA_START_FLAG),
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.RD_TX_DATA_WORD_VALID (RD_TX_DATA_WORD_VALID[(C_DATA_WIDTH/32)-1:0]),
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.RD_TX_DATA_END_FLAGS (RD_TX_DATA_END_FLAGS[(C_DATA_WIDTH/32)-1:0]),
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.RD_TX_DATA_PACKET_VALID (RD_TX_DATA_PACKET_VALID),
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// Inputs
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.WR_TX_DATA (wRdTxData),
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.WR_TX_DATA_VALID (wRdTxDataValid),
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.WR_TX_DATA_START_FLAG (wRdTxDataStartFlag),
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.WR_TX_DATA_WORD_VALID (wRdTxDataWordValid),
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.WR_TX_DATA_END_FLAGS (wRdTxDataEndFlags),
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.RD_TX_DATA_WORD_READY (RD_TX_DATA_WORD_READY),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN));
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endmodule
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// Local Variables:
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// verilog-library-directories:("." "../../../common/")
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// End:
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