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https://github.com/KastnerRG/riffa.git
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ad90d61584
Expanded DONE_RST into four signals, for each of the four engine interfaces. In the ultrascale engines, wired up all of the RST and DONE_RST signals. Quickly tested the logic in a power-on-reset like situation, no guarantees on graceful in-transmission resets. Classic engines will have to wait.
237 lines
12 KiB
Verilog
237 lines
12 KiB
Verilog
// ----------------------------------------------------------------------
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// Copyright (c) 2015, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Filename: tx_engine_ultrascale.v
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// Version: 1.0
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// Verilog Standard: Verilog-2001
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// Description: The TX Engine takes unformatted request and completions,
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// formats these packets into AXI packets for the Xilinx Core. These packets
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// must meet max-request, max-payload, and payload termination requirements (see
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// Read Completion Boundary). The TX Engine does not check these requirements
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// during operation, but may do so during simulation.
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//
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// This Engine is capable of operating at "line rate".
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// Author: Dustin Richmond (@darichmond)
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//-----------------------------------------------------------------------------
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`include "trellis.vh"
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`include "ultrascale.vh"
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module tx_engine_ultrascale
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#(parameter C_PCI_DATA_WIDTH = 128,
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parameter C_PIPELINE_INPUT = 1,
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parameter C_PIPELINE_OUTPUT = 0,
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parameter C_MAX_PAYLOAD_DWORDS = 64)
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(// Interface: Clocks
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input CLK,
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// Interface: Resets
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input RST_BUS, // Replacement for generic RST_IN
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input RST_LOGIC, // Addition for RIFFA_RST
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output DONE_TXC_RST,
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output DONE_TXR_RST,
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// Interface: Configuration
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input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
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// Interface: CC
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input S_AXIS_CC_TREADY,
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output S_AXIS_CC_TVALID,
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output S_AXIS_CC_TLAST,
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output [C_PCI_DATA_WIDTH-1:0] S_AXIS_CC_TDATA,
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output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_CC_TKEEP,
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output [`SIG_CC_TUSER_W-1:0] S_AXIS_CC_TUSER,
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// Interface: TXC Engine
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input TXC_DATA_VALID,
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input [C_PCI_DATA_WIDTH-1:0] TXC_DATA,
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input TXC_DATA_START_FLAG,
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input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_START_OFFSET,
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input TXC_DATA_END_FLAG,
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input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_END_OFFSET,
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output TXC_DATA_READY,
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input TXC_META_VALID,
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input [`SIG_FBE_W-1:0] TXC_META_FDWBE,
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input [`SIG_LBE_W-1:0] TXC_META_LDWBE,
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input [`SIG_LOWADDR_W-1:0] TXC_META_ADDR,
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input [`SIG_TYPE_W-1:0] TXC_META_TYPE,
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input [`SIG_LEN_W-1:0] TXC_META_LENGTH,
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input [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT,
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input [`SIG_TAG_W-1:0] TXC_META_TAG,
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input [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID,
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input [`SIG_TC_W-1:0] TXC_META_TC,
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input [`SIG_ATTR_W-1:0] TXC_META_ATTR,
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input TXC_META_EP,
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output TXC_META_READY,
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output TXC_SENT,
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// Interface: RQ
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input S_AXIS_RQ_TREADY,
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output S_AXIS_RQ_TVALID,
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output S_AXIS_RQ_TLAST,
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output [C_PCI_DATA_WIDTH-1:0] S_AXIS_RQ_TDATA,
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output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_RQ_TKEEP,
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output [`SIG_RQ_TUSER_W-1:0] S_AXIS_RQ_TUSER,
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// Interface: TXR Engine
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input TXR_DATA_VALID,
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input [C_PCI_DATA_WIDTH-1:0] TXR_DATA,
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input TXR_DATA_START_FLAG,
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input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
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input TXR_DATA_END_FLAG,
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input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
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output TXR_DATA_READY,
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input TXR_META_VALID,
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input [`SIG_FBE_W-1:0] TXR_META_FDWBE,
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input [`SIG_LBE_W-1:0] TXR_META_LDWBE,
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input [`SIG_ADDR_W-1:0] TXR_META_ADDR,
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input [`SIG_LEN_W-1:0] TXR_META_LENGTH,
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input [`SIG_TAG_W-1:0] TXR_META_TAG,
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input [`SIG_TC_W-1:0] TXR_META_TC,
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input [`SIG_ATTR_W-1:0] TXR_META_ATTR,
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input [`SIG_TYPE_W-1:0] TXR_META_TYPE,
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input TXR_META_EP,
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output TXR_META_READY,
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output TXR_SENT
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);
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localparam C_DEPTH_PACKETS = 10;
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/*AUTOWIRE*/
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/*AUTOINPUT*/
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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// End of automatics
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reg rTxcSent;
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reg rTxrSent;
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assign TXC_SENT = rTxcSent;
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assign TXR_SENT = rTxrSent;
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always @(posedge CLK) begin
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rTxcSent <= S_AXIS_CC_TLAST & S_AXIS_CC_TVALID & S_AXIS_CC_TREADY;
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rTxrSent <= S_AXIS_RQ_TLAST & S_AXIS_RQ_TVALID & S_AXIS_RQ_TREADY;
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end
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txr_engine_ultrascale
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#(/*AUTOINSTPARAM*/
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// Parameters
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.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
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.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
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.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
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.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
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.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS))
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txr_engine_inst
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(/*AUTOINST*/
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// Outputs
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.DONE_TXR_RST (DONE_TXR_RST),
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.S_AXIS_RQ_TVALID (S_AXIS_RQ_TVALID),
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.S_AXIS_RQ_TLAST (S_AXIS_RQ_TLAST),
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.S_AXIS_RQ_TDATA (S_AXIS_RQ_TDATA[C_PCI_DATA_WIDTH-1:0]),
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.S_AXIS_RQ_TKEEP (S_AXIS_RQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
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.S_AXIS_RQ_TUSER (S_AXIS_RQ_TUSER[`SIG_RQ_TUSER_W-1:0]),
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.TXR_DATA_READY (TXR_DATA_READY),
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.TXR_META_READY (TXR_META_READY),
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// Inputs
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.CLK (CLK),
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.RST_BUS (RST_BUS),
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.RST_LOGIC (RST_LOGIC),
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.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
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.S_AXIS_RQ_TREADY (S_AXIS_RQ_TREADY),
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.TXR_DATA_VALID (TXR_DATA_VALID),
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.TXR_DATA (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
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.TXR_DATA_START_FLAG (TXR_DATA_START_FLAG),
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.TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
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.TXR_DATA_END_FLAG (TXR_DATA_END_FLAG),
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.TXR_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
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.TXR_META_VALID (TXR_META_VALID),
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.TXR_META_FDWBE (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
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.TXR_META_LDWBE (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
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.TXR_META_ADDR (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
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.TXR_META_LENGTH (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
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.TXR_META_TAG (TXR_META_TAG[`SIG_TAG_W-1:0]),
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.TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]),
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.TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
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.TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
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.TXR_META_EP (TXR_META_EP));
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txc_engine_ultrascale
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#(
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/*AUTOINSTPARAM*/
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// Parameters
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.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
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.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
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.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
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.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
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.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS))
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txc_engine_inst
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(/*AUTOINST*/
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// Outputs
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.DONE_TXC_RST (DONE_TXC_RST),
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.S_AXIS_CC_TVALID (S_AXIS_CC_TVALID),
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.S_AXIS_CC_TLAST (S_AXIS_CC_TLAST),
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.S_AXIS_CC_TDATA (S_AXIS_CC_TDATA[C_PCI_DATA_WIDTH-1:0]),
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.S_AXIS_CC_TKEEP (S_AXIS_CC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
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.S_AXIS_CC_TUSER (S_AXIS_CC_TUSER[`SIG_CC_TUSER_W-1:0]),
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.TXC_DATA_READY (TXC_DATA_READY),
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.TXC_META_READY (TXC_META_READY),
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// Inputs
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.CLK (CLK),
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.RST_BUS (RST_BUS),
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.RST_LOGIC (RST_LOGIC),
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.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
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.S_AXIS_CC_TREADY (S_AXIS_CC_TREADY),
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.TXC_DATA_VALID (TXC_DATA_VALID),
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.TXC_DATA (TXC_DATA[C_PCI_DATA_WIDTH-1:0]),
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.TXC_DATA_START_FLAG (TXC_DATA_START_FLAG),
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.TXC_DATA_START_OFFSET (TXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
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.TXC_DATA_END_FLAG (TXC_DATA_END_FLAG),
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.TXC_DATA_END_OFFSET (TXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
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.TXC_META_VALID (TXC_META_VALID),
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.TXC_META_FDWBE (TXC_META_FDWBE[`SIG_FBE_W-1:0]),
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.TXC_META_LDWBE (TXC_META_LDWBE[`SIG_LBE_W-1:0]),
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.TXC_META_ADDR (TXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
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.TXC_META_TYPE (TXC_META_TYPE[`SIG_TYPE_W-1:0]),
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.TXC_META_LENGTH (TXC_META_LENGTH[`SIG_LEN_W-1:0]),
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.TXC_META_BYTE_COUNT (TXC_META_BYTE_COUNT[`SIG_BYTECNT_W-1:0]),
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.TXC_META_TAG (TXC_META_TAG[`SIG_TAG_W-1:0]),
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.TXC_META_REQUESTER_ID (TXC_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
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.TXC_META_TC (TXC_META_TC[`SIG_TC_W-1:0]),
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.TXC_META_ATTR (TXC_META_ATTR[`SIG_ATTR_W-1:0]),
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.TXC_META_EP (TXC_META_EP));
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endmodule
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