FPGA/riffa
1
0
Fork 0
mirror of https://github.com/KastnerRG/riffa.git synced 2025-01-30 23:02:54 +08:00
Code Issues Projects Releases Wiki Activity
riffa/fpga/riffa_hdl
History
Dustin Richmond c420b76c16 Finishing reset logic and testing/implementing across a wide swath of boards. 
Changes are mostly in the RX logic, where RST_IN was still used, though some new
logic (reset_extender) was added to riffa.v. Updated projects for: VC709, VC707,
ZC706 (partial), NetFPGA, ADM-7V3, ML605 (Still not working), AC701 (Untested)
and KC705 (Untested)
2015-08-12 16:16:27 -07:00
..
altera.vh
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
async_fifo_fwft.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
async_fifo.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
channel_32.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
channel_64.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
channel_128.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
channel.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
chnl_tester.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
counter.v
Fixed a small bit-width related issue in counter.v.
2015-07-15 16:44:50 -07:00
cross_domain_signal.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
demux.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
engine_layer.v
Finished wiring reset logic in the Engine Layer (untested)
2015-07-16 16:26:05 -07:00
ff.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
fifo_packer_32.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
fifo_packer_64.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
fifo_packer_128.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
fifo.v
Added a parameter C_VALUE to shiftreg.v and changed all declarations.
2015-07-15 17:26:00 -07:00
functions.vh
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
interrupt_controller.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
interrupt.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
mux.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
offset_flag_to_one_hot.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
offset_to_mask.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
one_hot_mux.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
pipeline.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
ram_1clk_1w_1r.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
ram_2clk_1w_1r.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
recv_credit_flow_ctrl.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
register.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
registers.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
reorder_queue_input.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
reorder_queue_output.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
reorder_queue.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
reset_controller.v
Adding graceful reset logic to the Ultrascale TX Engines
2015-07-22 17:29:35 -07:00
reset_extender.v
Finishing reset logic and testing/implementing across a wide swath of boards.
2015-08-12 16:16:27 -07:00
riffa.v
Finishing reset logic and testing/implementing across a wide swath of boards.
2015-08-12 16:16:27 -07:00
riffa.vh
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
rotate.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
rx_engine_classic.v
Finishing reset logic and testing/implementing across a wide swath of boards.
2015-08-12 16:16:27 -07:00
rx_engine_ultrascale.v
Finished wiring reset logic in the Engine Layer (untested)
2015-07-16 16:26:05 -07:00
rx_port_32.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
rx_port_64.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
rx_port_128.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
rx_port_channel_gate.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
rx_port_reader.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
rx_port_requester_mux.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
rxc_engine_128.v
Finishing reset logic and testing/implementing across a wide swath of boards.
2015-08-12 16:16:27 -07:00
rxc_engine_classic.v
Finishing reset logic and testing/implementing across a wide swath of boards.
2015-08-12 16:16:27 -07:00
rxc_engine_ultrascale.v
Finishing reset logic and testing/implementing across a wide swath of boards.
2015-08-12 16:16:27 -07:00
rxr_engine_128.v
Finishing reset logic and testing/implementing across a wide swath of boards.
2015-08-12 16:16:27 -07:00
rxr_engine_classic.v
Finishing reset logic and testing/implementing across a wide swath of boards.
2015-08-12 16:16:27 -07:00
rxr_engine_ultrascale.v
Finishing reset logic and testing/implementing across a wide swath of boards.
2015-08-12 16:16:27 -07:00
schedules.vh
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
scsdpram.v
Added a parameter C_VALUE to shiftreg.v and changed all declarations.
2015-07-15 17:26:00 -07:00
sg_list_reader_32.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
sg_list_reader_64.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
sg_list_reader_128.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
sg_list_requester.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
shiftreg.v
Added a parameter C_VALUE to shiftreg.v and changed all declarations.
2015-07-15 17:26:00 -07:00
sync_fifo.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
syncff.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tlp.vh
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
translation_altera.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
translation_xilinx.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
trellis.vh
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_alignment_pipeline.v
Adding timing improvements to tx_alignment pipeline.
2015-07-27 19:26:55 -07:00
tx_data_fifo.v
Fixed two bugs, one in riffa.v, one in tx_data_fifo.v
2015-07-30 13:35:48 -07:00
tx_data_pipeline.v
Fixing a bug in the tx_data_fifo where the data fifo was not large enough.
2015-07-29 08:33:11 -07:00
tx_data_shift.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_engine_classic.v
Finalized reset logic in the classic engines (see previous commit)
2015-07-23 09:56:44 -07:00
tx_engine_selector.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_engine_ultrascale.v
Finished wiring reset logic in the Engine Layer (untested)
2015-07-16 16:26:05 -07:00
tx_engine.v
Fixed two bugs, one in riffa.v, one in tx_data_fifo.v
2015-07-30 13:35:48 -07:00
tx_hdr_fifo.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_multiplexer_32.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_multiplexer_64.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_multiplexer_128.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_multiplexer.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_port_32.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_port_64.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_port_128.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_port_buffer_32.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_port_buffer_64.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_port_buffer_128.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_port_channel_gate_32.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_port_channel_gate_64.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_port_channel_gate_128.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_port_monitor_32.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_port_monitor_64.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_port_monitor_128.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_port_writer.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
txc_engine_classic.v
Finalized reset logic in the classic engines (see previous commit)
2015-07-23 09:56:44 -07:00
txc_engine_ultrascale.v
Finalized reset logic in the classic engines (see previous commit)
2015-07-23 09:56:44 -07:00
txr_engine_classic.v
Finalized reset logic in the classic engines (see previous commit)
2015-07-23 09:56:44 -07:00
txr_engine_ultrascale.v
Finalized reset logic in the classic engines (see previous commit)
2015-07-23 09:56:44 -07:00
types.vh
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
ultrascale.vh
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
widths.vh
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
xilinx.vh
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00