mirror of
https://github.com/KastnerRG/riffa.git
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5058a758fc
This does not fix the user bug, which occurs in the 64-bit interface. I suspect this is a data under-read/over-read error in the data fifo but I have yet to confirm it.
517 lines
25 KiB
Verilog
517 lines
25 KiB
Verilog
// ----------------------------------------------------------------------
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// Copyright (c) 2015, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Filename: tx_alignment_pipeline
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// Version: 1.0
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// Verilog Standard: Verilog-2001
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//
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// Description: The TX alignment pipeline takes a formatted header and data and
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// "aligns" them to create a formatted PKT. The aligner is used in both the TXC
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// and TXR engines.
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//
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// The data interface (TX_DATA) is an interface for N 32-bit FIFOs, where N =
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// (C_DATA_WIDTH/32). The START_FLAG signal indicates that the first dword of
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// a packet is in FIFO 0 (TX_DATA[31:0]). Each FIFO interface also contains an
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// END_FLAG signal in the END_FLAGS bus. When a bit in END_FLAGS bus is asserted,
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// its corresponding fifo contains the last dword of data for the current
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// packet. START_FLAG, END_FLAG and DATA are all qualified by the VALID signal,
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// and read by the READY signal.
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//
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// The header interface (TX_HDR) presents the entire header in a single cycle on a
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// fifo-like read-interface. The interface also contains the metadata signals
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// NOPAYLOAD, ABLANKS, and LEN. NOPAYLOAD indicates that the header is not
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// associated with a payload. ABLANKS indicates how many blanks are inserted
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// between header and payload for address alignment. LEN indicates the length of
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// the header (in DWORDS). The previous two signals determine the multiplexer
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// schedule.
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//
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// The aligner is built around N alignment muxes that chose between header and
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// data. The aligner uses a multiplexer ROM-based schedule to determine the
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// outputs of the alignment muxes. This schedule is listed in the schedules.vh
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// include file. It initializes the wSchedule ROM. The ROM is indexed by the
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// concatenation of ABLANKS, (Header) LEN, and a saturating counter. The
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// saturating counter stops when the selection bits for all multiplexers reach a
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// steady state.
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//
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// See schedules.vh for more information regarding the wSchedule and wTxMuxInputs
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// arrays.
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//
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// Plans:
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// - At some point in the future, wSchedule and wTxMuxInputs should be set by
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// initialization functions to improve extensibility and reusability, but it may
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// decrease readability.
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//
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// - (with above) Right now the alignment pipeline works for devices that have 3
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// or 4 header dwords and insert a maximum of one alignment blank. To extend
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// this, wScheduleSelect, and C_MAX_SCHEDULE_LENGTH need to be
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// changed. wSchedule select needs to incorporate additional information bits
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// (including the minimum header length). and C_MAX_SCHEDULE_LENGTH must be
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// calculated using a function (see previous note)
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//
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// Author: Dustin Richmond (@darichmond)
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//----------------------------------------------------------------------------
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`timescale 1ns/1ns
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`include "trellis.vh" // Defines the user-facing signal widths.
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module tx_alignment_pipeline
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#(parameter C_PIPELINE_OUTPUT = 1,
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parameter C_PIPELINE_DATA_INPUT = 1,
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parameter C_PIPELINE_HDR_INPUT = 1,
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parameter C_USE_COMPUTE_REG = 1,
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parameter C_USE_READY_REG = 1,
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parameter C_DATA_WIDTH = 128,
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parameter C_MAX_HDR_WIDTH = 128,
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parameter C_VENDOR = "ALTERA")
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(// Interface: Clocks
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input CLK,
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// Interface: Reset
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input RST_IN,
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// Interface: TX DATA FIFOS
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input [(C_DATA_WIDTH/32)-1:0] TX_DATA_WORD_VALID,
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input [C_DATA_WIDTH-1:0] TX_DATA,
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input TX_DATA_START_FLAG,
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input TX_DATA_PACKET_VALID,
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input [(C_DATA_WIDTH/32)-1:0] TX_DATA_END_FLAGS,
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output [(C_DATA_WIDTH/32)-1:0] TX_DATA_WORD_READY,
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// Interface: TX HDR
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input TX_HDR_VALID,
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input [C_MAX_HDR_WIDTH-1:0] TX_HDR,
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input [`SIG_LEN_W-1:0] TX_HDR_PAYLOAD_LEN,
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input [`SIG_NONPAY_W-1:0] TX_HDR_NONPAY_LEN,
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input [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,
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input TX_HDR_NOPAYLOAD,
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output TX_HDR_READY,
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// TX Interface (Unified)
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input TX_PKT_READY,
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output [C_DATA_WIDTH-1:0] TX_PKT,
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output TX_PKT_START_FLAG,
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output [clog2s(C_DATA_WIDTH/32)-1:0] TX_PKT_START_OFFSET,
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output TX_PKT_END_FLAG,
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output [clog2s(C_DATA_WIDTH/32)-1:0] TX_PKT_END_OFFSET,
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output TX_PKT_VALID);
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localparam C_OFFSET_WIDTH = clog2s(C_DATA_WIDTH/32);
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localparam C_AGGREGATE_WIDTH = (C_DATA_WIDTH+C_MAX_HDR_WIDTH);
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localparam C_MASK_WIDTH = (C_DATA_WIDTH/32);
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localparam C_NUM_MUXES = (C_DATA_WIDTH/32);
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localparam C_MUX_INPUTS = (C_DATA_WIDTH == 32)?5:4;
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localparam C_CLOG_MUX_INPUTS = clog2s(C_MUX_INPUTS);
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localparam C_MAX_SCHEDULE = (C_DATA_WIDTH == 256)? 2 : (C_DATA_WIDTH == 128)? 3: (C_DATA_WIDTH == 64)? 4: (C_DATA_WIDTH == 32)? 6 : 0;
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localparam C_CLOG_MAX_SCHEDULE = clog2s(C_MAX_SCHEDULE);
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genvar i;
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// Wires from the data interface input registers
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wire [(C_DATA_WIDTH/32)-1:0] wTxDataWordValid;
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wire wTxDataPacketValid;
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wire [(C_DATA_WIDTH/32)-1:0] wTxDataWordReady;
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wire [C_DATA_WIDTH-1:0] wTxData;
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wire wTxDataStartFlag;
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wire [(C_DATA_WIDTH/32)-1:0] wTxDataEndFlags;
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wire [clog2s(C_DATA_WIDTH/32)-1:0] wTxDataEndOffset;
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// Wires from the header interface input register
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wire wTxHdrReady,_wTxHdrReady,__wTxHdrReady;
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wire [C_MAX_HDR_WIDTH -1:0] wTxHdr,_wTxHdr,__wTxHdr;
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wire wTxHdrValid,_wTxHdrValid,__wTxHdrValid;
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wire wTxHdrNoPayload,_wTxHdrNoPayload,__wTxHdrNoPayload;
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wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen,_wTxHdrPayloadLen,__wTxHdrPayloadLen;
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wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen,_wTxHdrNonpayLen,__wTxHdrNonpayLen;
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wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen,_wTxHdrPacketLen,__wTxHdrPacketLen;
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wire [`SIG_PACKETLEN_W:0] __wTxHdrPacketLenMinus1;
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wire [C_MUX_INPUTS-1:0] __wTxHdrPacketMask;
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wire [C_MUX_INPUTS-1:0] __wTxHdrLenMask;
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// wSchedule is the array containing all of the schedules for each mux and ready signal
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// wSchedule is indexed by the concatenation {Insert Blanks, Header Length, Saturating Counter}
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wire [C_CLOG_MUX_INPUTS-1:0] wSchedule[C_NUM_MUXES-1:0][(1<<(3+C_CLOG_MAX_SCHEDULE))-1:0];
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// Create an array of mux selects, and a bus of ready signals. The ready
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// signals are indicate when a dword is being read from the input fifo and
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// are statically determined in the schedules.vh file
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wire [(3+C_CLOG_MAX_SCHEDULE)-1:0] wScheduleSelect;
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wire [C_NUM_MUXES-1:0] __wTxHdrStartEndReady,_wTxHdrStartEndReady;
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wire [C_NUM_MUXES-1:0] __wTxHdrStartReady,_wTxHdrStartReady;
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wire [C_NUM_MUXES-1:0] __wTxHdrEndReady,_wTxHdrEndReady;
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wire [C_NUM_MUXES-1:0] __wTxHdrSteadyStateReady,_wTxHdrSteadyStateReady;
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wire [1:0] wReadyMuxSelect;
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wire [C_NUM_MUXES-1:0] wReadyMux[3:0];
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// Aggreate the header and the current data inputs into an array.
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wire [31:0] wAggregate[C_AGGREGATE_WIDTH/32-1:0];
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wire [32*C_MUX_INPUTS-1:0] wTxMuxInputs[C_NUM_MUXES-1:0];
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wire [(C_CLOG_MUX_INPUTS*C_NUM_MUXES)-1:0] wTxMuxSelect,_wTxMuxSelect;
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wire [C_NUM_MUXES-1:0] wTxMuxSelectDataReady,_wTxMuxSelectDataReady;
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wire [C_NUM_MUXES-1:0] wTxMuxSelectDataReadyAndPayload,_wTxMuxSelectDataReadyAndPayload;
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wire wTxMuxSelectDataEndFlag,_wTxMuxSelectDataEndFlag;
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wire wTxMuxSelectDataStartFlag,_wTxMuxSelectDataStartFlag;
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wire wTxMuxSelectPktStartFlag,_wTxMuxSelectPktStartFlag;
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wire wTxMuxSelectReady,_wTxMuxSelectReady;
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wire wTxMuxSelectValid,_wTxMuxSelectValid;
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// Wires from the output of the muxes to the input of the output register stage
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// wTxPktReady is asserted when a packet is complete
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wire wTxPktReady;
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wire wTxPktValid;
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wire [C_DATA_WIDTH-1:0] wTxPkt;
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wire wTxPktStartFlag;
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wire wTxPktEndFlag;
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wire [C_OFFSET_WIDTH:0] wTxPktEndOffset; // An additional bit for addition overflow
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// Saturating Counter Wires
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wire wSatCtrEnable;
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wire wSatCtrReset;
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wire [C_CLOG_MAX_SCHEDULE-1:0] wSatCtr;
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// Packet Cycle Counter Wires
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wire wPktCtrEnable;
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wire wPktCtrReset;
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wire [`SIG_PACKETLEN_W-1:0] wPktCtr;
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wire wCounterReset;
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`include "schedules.vh"
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// Assignments for the Input Register Stage
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assign __wTxHdrPacketLenMinus1 = __wTxHdrPacketLen - 1;
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assign __wTxHdrSteadyStateReady = {C_NUM_MUXES{1'b1}};
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assign __wTxHdrStartReady = {C_NUM_MUXES{1'b1}} >> __wTxHdrNonpayLen[C_OFFSET_WIDTH-1:0];
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//assign __wTxHdrEndReady = __wTxHdrPacketMask ROTATE-RIGHT __wTxHdrNonpayLen[C_OFFSET_WIDTH-1:0];
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assign __wTxHdrStartEndReady = __wTxHdrLenMask;
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// Assignments for the computation stage
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// Counter logic
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assign wCounterReset = _wTxMuxSelectDataEndFlag & _wTxMuxSelectReady;
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assign wSatCtrReset = RST_IN | wCounterReset;
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assign wSatCtrEnable = _wTxMuxSelectReady & _wTxMuxSelectValid;
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assign wPktCtrReset = RST_IN | wCounterReset;
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assign wPktCtrEnable = _wTxMuxSelectReady & _wTxMuxSelectValid;
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assign wScheduleSelect = {_wTxHdrNonpayLen[2:0],wSatCtr[C_CLOG_MAX_SCHEDULE-1:0]};
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// Ready Mux Logic
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assign wReadyMuxSelect[0] = _wTxMuxSelectDataStartFlag;
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assign wReadyMuxSelect[1] = _wTxMuxSelectDataEndFlag;
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assign wReadyMux[0] = _wTxHdrSteadyStateReady;
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assign wReadyMux[1] = _wTxHdrStartReady;
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assign wReadyMux[2] = _wTxHdrEndReady;
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assign wReadyMux[3] = _wTxHdrStartEndReady;
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assign _wTxMuxSelectValid = _wTxHdrValid;
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assign _wTxMuxSelectDataReady = wReadyMux[wReadyMuxSelect] & {C_NUM_MUXES{(wPktCtr >= _wTxHdrNonpayLen[`SIG_NONPAY_W-1:clog2s(C_NUM_MUXES)])}};
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assign _wTxMuxSelectDataReadyAndPayload = wReadyMux[wReadyMuxSelect] &
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{C_NUM_MUXES{(wPktCtr >= _wTxHdrNonpayLen[`SIG_NONPAY_W-1:clog2s(C_NUM_MUXES)])}} &
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{C_NUM_MUXES{~_wTxHdrNoPayload}} &
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{C_NUM_MUXES{_wTxHdrValid}};
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assign _wTxMuxSelectPktStartFlag = wPktCtr == 0;
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assign _wTxMuxSelectDataStartFlag = wPktCtr == _wTxHdrNonpayLen[`SIG_NONPAY_W-1:clog2s(C_NUM_MUXES)];
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assign _wTxMuxSelectDataEndFlag = ({wPktCtr,{clog2s(C_NUM_MUXES){1'b0}}} + C_NUM_MUXES) >= _wTxHdrPacketLen;// TODO: Simplify
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// Assignments for the ready stage
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assign wTxHdrReady = (wTxMuxSelectDataEndFlag & wTxMuxSelectValid & wTxMuxSelectReady) | ~wTxMuxSelectValid;
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assign wTxMuxSelectReady = (wTxPktReady & wTxHdrNoPayload) |
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(wTxPktReady & wTxDataPacketValid) |
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(~wTxMuxSelectValid);
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assign wTxPktStartFlag = wTxMuxSelectPktStartFlag;
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assign wTxPktEndFlag = wTxMuxSelectDataEndFlag;
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assign wTxPktEndOffset = wTxHdrPacketLen[C_OFFSET_WIDTH-1:0]-1; // TODO: Retime -1?
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assign wTxPktValid = wTxMuxSelectValid & (wTxHdrNoPayload | (~wTxHdrNoPayload & wTxDataPacketValid));
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// assign wTxDataWordReady = wTxMuxSelectDataReady & {C_NUM_MUXES{wTxPktReady & wTxMuxSelectValid & wTxDataPacketValid}};
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assign wTxDataWordReady = wTxMuxSelectDataReadyAndPayload & {C_NUM_MUXES{wTxPktReady & wTxDataPacketValid}};
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// Assignments for the output stage
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assign TX_PKT_START_OFFSET = {C_OFFSET_WIDTH{1'b0}};
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/*See comment block at start of module*/
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generate
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for(i = 0 ; i < C_NUM_MUXES ; i = i + 1) begin : muxes
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assign _wTxMuxSelect[i*C_CLOG_MUX_INPUTS +: C_CLOG_MUX_INPUTS] = wSchedule[i][wScheduleSelect];
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end
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endgenerate
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offset_to_mask
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#(// Parameters
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.C_MASK_SWAP (0),
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.C_MASK_WIDTH (C_NUM_MUXES)
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/*AUTOINSTPARAM*/)
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packet_mask
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(
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// Outputs
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.MASK (__wTxHdrPacketMask),
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// Inputs
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.OFFSET_ENABLE (1),
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.OFFSET (__wTxHdrPacketLenMinus1[clog2s(C_NUM_MUXES)-1:0])
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/*AUTOINST*/);
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offset_to_mask
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#(// Parameters
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.C_MASK_SWAP (0),
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.C_MASK_WIDTH (C_NUM_MUXES)
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/*AUTOINSTPARAM*/)
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len_mask
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(// Outputs
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.MASK (__wTxHdrLenMask),
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// Inputs
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.OFFSET_ENABLE (1),
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.OFFSET (__wTxHdrPayloadLen[clog2s(C_NUM_MUXES)-1:0]-1)
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/*AUTOINST*/);
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rotate
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#(// Parameters
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.C_DIRECTION ("RIGHT"),
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.C_WIDTH (C_NUM_MUXES)
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/*AUTOINSTPARAM*/)
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rot_inst
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(// Outputs
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.RD_DATA (__wTxHdrEndReady),
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// Inputs
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.WR_DATA (__wTxHdrPacketMask),
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.WR_SHIFTAMT (__wTxHdrNonpayLen[C_OFFSET_WIDTH-1:0])
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/*AUTOINST*/);
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pipeline
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#(// Parameters
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.C_DEPTH (C_PIPELINE_HDR_INPUT?1:0),
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.C_WIDTH (C_MAX_HDR_WIDTH + `SIG_NONPAY_W + `SIG_PACKETLEN_W + `SIG_LEN_W + 1),
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.C_USE_MEMORY (0)
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/*AUTOINSTPARAM*/)
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hdr_input_reg
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(// Outputs
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.WR_DATA_READY (TX_HDR_READY),
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.RD_DATA ({__wTxHdr,__wTxHdrNonpayLen,__wTxHdrPacketLen,__wTxHdrPayloadLen,__wTxHdrNoPayload}),
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.RD_DATA_VALID (__wTxHdrValid),
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// Inputs
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.WR_DATA ({TX_HDR,TX_HDR_NONPAY_LEN,TX_HDR_PACKET_LEN,TX_HDR_PAYLOAD_LEN,TX_HDR_NOPAYLOAD}),
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.WR_DATA_VALID (TX_HDR_VALID),
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.RD_DATA_READY (__wTxHdrReady),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN));
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pipeline
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#(// Parameters
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.C_DEPTH (C_USE_COMPUTE_REG?1:0),
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.C_WIDTH (C_MAX_HDR_WIDTH + `SIG_NONPAY_W + `SIG_PACKETLEN_W + `SIG_LEN_W + 1 + 4*C_MASK_WIDTH),
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.C_USE_MEMORY (0)
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/*AUTOINSTPARAM*/)
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compute_reg
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(// Outputs
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.WR_DATA_READY (__wTxHdrReady),
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.RD_DATA ({_wTxHdr,_wTxHdrNonpayLen,_wTxHdrPacketLen,_wTxHdrPayloadLen,_wTxHdrNoPayload,
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_wTxHdrSteadyStateReady,_wTxHdrStartReady,_wTxHdrEndReady,_wTxHdrStartEndReady}),
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.RD_DATA_VALID (_wTxHdrValid),
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// Inputs
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.WR_DATA ({__wTxHdr,__wTxHdrNonpayLen,__wTxHdrPacketLen,__wTxHdrPayloadLen,__wTxHdrNoPayload,
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__wTxHdrSteadyStateReady,__wTxHdrStartReady,__wTxHdrEndReady,__wTxHdrStartEndReady}),
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.WR_DATA_VALID (__wTxHdrValid),
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.RD_DATA_READY (_wTxMuxSelectDataEndFlag & _wTxMuxSelectReady),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN));
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pipeline
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#(// Parameters
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.C_DEPTH (C_USE_READY_REG?1:0),
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.C_WIDTH (C_MAX_HDR_WIDTH + `SIG_NONPAY_W + `SIG_PACKETLEN_W + `SIG_LEN_W + 1),
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.C_USE_MEMORY (0)
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/*AUTOINSTPARAM*/)
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ready_reg
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(// Outputs
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.WR_DATA_READY (_wTxHdrReady),
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.RD_DATA ({wTxHdr,wTxHdrNonpayLen,wTxHdrPacketLen,wTxHdrPayloadLen,wTxHdrNoPayload}),
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.RD_DATA_VALID (wTxHdrValid),
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// Inputs
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.WR_DATA ({_wTxHdr,_wTxHdrNonpayLen,_wTxHdrPacketLen,_wTxHdrPayloadLen,_wTxHdrNoPayload}),
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.WR_DATA_VALID (_wTxHdrValid),
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.RD_DATA_READY (wTxHdrReady),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN));
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pipeline
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#(// Parameters
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.C_DEPTH (C_USE_READY_REG?1:0),
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.C_WIDTH (2*C_NUM_MUXES + C_CLOG_MUX_INPUTS * C_NUM_MUXES + 3),
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.C_USE_MEMORY (0)
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/*AUTOINSTPARAM*/)
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select_reg
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(// Outputs
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.WR_DATA_READY (_wTxMuxSelectReady),
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.RD_DATA ({wTxMuxSelectDataReady,wTxMuxSelect,
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wTxMuxSelectDataEndFlag,wTxMuxSelectDataStartFlag,
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wTxMuxSelectPktStartFlag,
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wTxMuxSelectDataReadyAndPayload}),
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.RD_DATA_VALID (wTxMuxSelectValid),
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// Inputs
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.WR_DATA ({_wTxMuxSelectDataReady,_wTxMuxSelect,
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_wTxMuxSelectDataEndFlag,_wTxMuxSelectDataStartFlag,
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_wTxMuxSelectPktStartFlag,
|
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_wTxMuxSelectDataReadyAndPayload}),
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.WR_DATA_VALID (_wTxMuxSelectValid),
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.RD_DATA_READY (wTxMuxSelectReady),
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/*AUTOINST*/
|
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN));
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|
|
|
counter
|
|
#(// Parameters
|
|
.C_MAX_VALUE (C_MAX_SCHEDULE-1),
|
|
.C_SAT_VALUE (C_MAX_SCHEDULE-1),
|
|
.C_RST_VALUE (0)
|
|
/*AUTOINSTPARAM*/)
|
|
satctr_inst
|
|
(// Outputs
|
|
.VALUE (wSatCtr),
|
|
// Inputs
|
|
.RST_IN (wSatCtrReset),
|
|
.ENABLE (wSatCtrEnable),
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.CLK (CLK));
|
|
|
|
counter
|
|
#(// Parameters
|
|
.C_MAX_VALUE (1<<`SIG_PACKETLEN_W),
|
|
.C_SAT_VALUE (1<<`SIG_PACKETLEN_W + 1), // Never saturate
|
|
.C_RST_VALUE (0)
|
|
/*AUTOINSTPARAM*/)
|
|
pktctr_inst
|
|
(// Outputs
|
|
.VALUE (wPktCtr),
|
|
// Inputs
|
|
.RST_IN (wPktCtrReset),
|
|
.ENABLE (wPktCtrEnable),
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.CLK (CLK));
|
|
|
|
generate
|
|
for( i = 0 ; i < C_MAX_HDR_WIDTH/32 ; i = i + 1) begin : gen_aggregate
|
|
assign wAggregate[i] = wTxHdr[i*32 +: 32];
|
|
end
|
|
|
|
pipeline
|
|
#(// Parameters
|
|
.C_DEPTH (C_PIPELINE_DATA_INPUT?1:0),
|
|
.C_WIDTH (1),
|
|
.C_USE_MEMORY (0)
|
|
/*AUTOINSTPARAM*/)
|
|
packet_valid_register
|
|
(// Outputs
|
|
.WR_DATA_READY (),
|
|
.RD_DATA (),
|
|
.RD_DATA_VALID (wTxDataPacketValid),
|
|
// Inputs
|
|
.WR_DATA (),
|
|
.WR_DATA_VALID (TX_DATA_PACKET_VALID),
|
|
.RD_DATA_READY (~wTxDataPacketValid |
|
|
((wTxDataEndFlags & wTxDataWordReady) != 0)),
|
|
// TODO: End flag read? This is odd, you want to read when there is not a valid packet
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.CLK (CLK),
|
|
.RST_IN (RST_IN));
|
|
for( i = 0; i < C_NUM_MUXES ; i = i + 1) begin : gen_data_input_regs
|
|
assign wAggregate[i + C_MAX_HDR_WIDTH/32] = wTxData[32*i +: 32];
|
|
pipeline
|
|
#(// Parameters
|
|
.C_DEPTH (C_PIPELINE_DATA_INPUT?1:0),
|
|
.C_WIDTH (32 + 1),
|
|
.C_USE_MEMORY (0)
|
|
/*AUTOINSTPARAM*/)
|
|
data_register_
|
|
(// Outputs
|
|
.WR_DATA_READY (TX_DATA_WORD_READY[i]),
|
|
.RD_DATA ({wTxData[32*i +: 32],
|
|
wTxDataEndFlags[i]}),
|
|
.RD_DATA_VALID (wTxDataWordValid[i]),
|
|
// Inputs
|
|
.WR_DATA ({TX_DATA[32*i +: 32],
|
|
TX_DATA_END_FLAGS[i] & TX_DATA_WORD_VALID[i]}),
|
|
.WR_DATA_VALID (TX_DATA_WORD_VALID[i]),
|
|
.RD_DATA_READY (wTxDataWordReady[i]),
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.CLK (CLK),
|
|
.RST_IN (RST_IN));
|
|
end
|
|
|
|
for( i = 0 ; i < C_NUM_MUXES ; i = i + 1) begin : gen_packet_format_multiplexers
|
|
mux
|
|
#(// Parameters
|
|
.C_NUM_INPUTS (C_MUX_INPUTS),
|
|
.C_CLOG_NUM_INPUTS (C_CLOG_MUX_INPUTS),
|
|
.C_WIDTH (32),
|
|
.C_MUX_TYPE ("SELECT")
|
|
/*AUTOINSTPARAM*/)
|
|
dw_mux_
|
|
(// Outputs
|
|
.MUX_OUTPUT (wTxPkt[32*i +: 32]),
|
|
// Inputs
|
|
.MUX_INPUTS (wTxMuxInputs[i]),
|
|
.MUX_SELECT (wTxMuxSelect[i*C_CLOG_MUX_INPUTS +: C_CLOG_MUX_INPUTS])
|
|
/*AUTOINST*/);
|
|
end
|
|
endgenerate
|
|
|
|
pipeline
|
|
#(// Parameters
|
|
.C_DEPTH (C_PIPELINE_OUTPUT?1:0),
|
|
.C_WIDTH (C_DATA_WIDTH + 2 + C_OFFSET_WIDTH),
|
|
.C_USE_MEMORY (0)
|
|
/*AUTOINSTPARAM*/)
|
|
output_register_inst
|
|
(// Outputs
|
|
.WR_DATA_READY (wTxPktReady),
|
|
.RD_DATA ({TX_PKT,TX_PKT_START_FLAG,TX_PKT_END_FLAG,TX_PKT_END_OFFSET}),
|
|
.RD_DATA_VALID (TX_PKT_VALID),
|
|
// Inputs
|
|
.WR_DATA ({wTxPkt,wTxPktStartFlag,wTxPktEndFlag,wTxPktEndOffset[C_OFFSET_WIDTH-1:0]}),
|
|
.WR_DATA_VALID (wTxPktValid),
|
|
.RD_DATA_READY (TX_PKT_READY),
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.CLK (CLK),
|
|
.RST_IN (RST_IN));
|
|
|
|
endmodule
|
|
// Local Variables:
|
|
// verilog-library-directories:("." "../../common/")
|
|
// End:
|