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327 lines
13 KiB
Verilog
327 lines
13 KiB
Verilog
// ----------------------------------------------------------------------
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// Copyright (c) 2015, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Filename: tx_data_shift.v
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// Version: 1.0
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// Verilog Standard: Verilog-2001
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//
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// Description: The TX Data Shift module takes arbitrarily 32-bit aligned data
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// from the WR_TX_DATA interface and shifts the data so that it is 0-bit aligned
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// on the output RD_TX_DATA interface. The VALID, END_OFFSET, and END_FLAG signal
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// in the WR_TX_DATA interface are replaced by WORD_VALID and END_FLAGS signals in
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// the RD_TX_DATA interface. Each bit in the WORD_VALID bus indicates that the
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// corresponding dword in the RD_TX_DATA bus is valid. Each bit in the END_FLAGS
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// bus indicates that the end of the payload occurs at the corresponding dword in
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// the RD_TX_DATA bus.
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//
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// The core of the TX_DATA_SHIFT module is a set of N multiplexers, where N =
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// (C_DATA_WIDTH/32). The multiplexers are surrounded by a set of optional
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// input and output registers with output wires wWrTxData* and input wires
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// wRdTxData*. Each register in the array rMuxSelect choses which mux input
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// desplay on the mux output. The values of the registers are set based on the
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// value of wWrTxDataStartOffset. These registers are enabled when
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// wWrTxDataStartFlag is 1 and their value set based on the value of
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// wWrTxDataStartOffset.
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//
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// Each bit in the VALID bus is determined by the result of two masks,
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// wRdTxEndFlagMask and wRdTxStartFlagMask, to make wRdTxDataValid. The start flag
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// mask is active when wWrTxDataStartFlag is 1, based on wWrTxDataStartOffset. The
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// end flag mask is active when wWrTxDataEndFlag is 1, based on
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// wWrTxDataEndOffset.
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//
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// TODO:
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// - Using WORD_VALID is a little bit confusing. I should bring back VALID as well
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// - WORD_VALID should be DWORD_VALID
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// - Use a uniform naming scheme for C_DATA_WIDTH/32
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// - Is there a more efficient way to implement the wRdTxStartMaskFlag? Perhaps using the reset of a register?
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// Author: Dustin Richmond (@darichmond)
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//-----------------------------------------------------------------------------
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`timescale 1ns/1ns
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`include "trellis.vh"
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module tx_data_shift
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#(
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parameter C_PIPELINE_OUTPUT = 1,
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parameter C_PIPELINE_INPUT = 1,
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parameter C_DATA_WIDTH = 128,
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parameter C_VENDOR = "ALTERA"
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)
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(
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// Interface: Clocks
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input CLK,
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// Interface: Reset
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input RST_IN,
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// Interface: WR TX DATA
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input WR_TX_DATA_VALID,
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input [C_DATA_WIDTH-1:0] WR_TX_DATA,
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input WR_TX_DATA_START_FLAG,
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input [clog2s(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_START_OFFSET,
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input WR_TX_DATA_END_FLAG,
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input [clog2s(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_END_OFFSET,
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output WR_TX_DATA_READY,
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// Interface: RD TX DATA
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input RD_TX_DATA_READY,
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output [C_DATA_WIDTH-1:0] RD_TX_DATA,
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output RD_TX_DATA_START_FLAG,
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output [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_WORD_VALID,
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output [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_END_FLAGS,
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output RD_TX_DATA_VALID
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);
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localparam C_ROTATE_BITS = clog2s(C_DATA_WIDTH/32);
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localparam C_NUM_MUXES = (C_DATA_WIDTH/32);
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localparam C_SELECT_WIDTH = C_DATA_WIDTH/32;
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localparam C_MASK_WIDTH = C_DATA_WIDTH/32;
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localparam C_AGGREGATE_WIDTH = C_DATA_WIDTH;
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genvar i;
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wire wWrTxDataValid;
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wire [C_DATA_WIDTH-1:0] wWrTxData;
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wire wWrTxDataStartFlag;
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wire [clog2s(C_DATA_WIDTH/32)-1:0] wWrTxDataStartOffset;
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wire wWrTxDataEndFlag;
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wire [clog2s(C_DATA_WIDTH/32)-1:0] wWrTxDataEndOffset;
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wire [(C_DATA_WIDTH/32)-1:0] wWrTxEndFlagMask;
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wire [(C_DATA_WIDTH/32)-1:0] wWrTxDataEndFlags;
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wire wWrTxDataReady;
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wire wRdTxDataReady;
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wire [C_DATA_WIDTH-1:0] wRdTxData;
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wire wRdTxDataStartFlag;
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wire [(C_DATA_WIDTH/32)-1:0] wRdTxDataEndFlags;
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wire [(C_DATA_WIDTH/32)-1:0] wRdTxDataWordValid;
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wire [(C_DATA_WIDTH/32)-1:0] wRdTxStartFlagMask;
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wire [(C_DATA_WIDTH/32)-1:0] wRdTxEndFlagMask;
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wire wRdTxDataValid;
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// wSelectDefault is the default select value for each mux, 1 << i where i
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// is the mux/dword index.
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wire [C_SELECT_WIDTH-1:0] wSelectDefault[C_NUM_MUXES-1:0];
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// wSelectRotated is the value the select for each mux after the data's
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// start offset has been applied and until the end flag is seen.
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wire [C_SELECT_WIDTH-1:0] wSelectRotated[C_NUM_MUXES-1:0];
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reg [C_SELECT_WIDTH-1:0] rMuxSelect[C_NUM_MUXES-1:0],_rMuxSelect[C_NUM_MUXES-1:0];
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reg [clog2s(C_DATA_WIDTH/32)-1:0] rStartOffset,_rStartOffset;
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assign wWrTxDataReady = wRdTxDataReady;
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assign wRdTxStartFlagMask = wWrTxDataStartFlag ?
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{(C_DATA_WIDTH/32){1'b1}} >> wWrTxDataStartOffset:
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{(C_DATA_WIDTH/32){1'b1}};
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assign wRdTxDataWordValid = wRdTxEndFlagMask & wRdTxStartFlagMask;
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assign wRdTxDataStartFlag = wWrTxDataStartFlag;
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assign wRdTxDataValid = wWrTxDataValid;
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generate
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for (i = 0; i < C_NUM_MUXES; i = i + 1) begin : gen_mux_default
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assign wSelectDefault[i] = (1 << i);
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end
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endgenerate
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always @(*) begin
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_rStartOffset = WR_TX_DATA_START_OFFSET;
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end
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always @(posedge CLK) begin
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if(WR_TX_DATA_READY & WR_TX_DATA_START_FLAG & WR_TX_DATA_VALID) begin
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rStartOffset <= _rStartOffset;
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end
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end
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generate
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for (i = 0; i < C_NUM_MUXES; i = i + 1) begin : gen_mux_select
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always @(*) begin
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_rMuxSelect[i] = wSelectRotated[i];
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end
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always @(posedge CLK) begin
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if(WR_TX_DATA_READY & WR_TX_DATA_START_FLAG) begin
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rMuxSelect[i] <= _rMuxSelect[i];
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end
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end
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end
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endgenerate
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pipeline
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#(// Parameters
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.C_WIDTH (C_DATA_WIDTH+2*(1+clog2s(C_DATA_WIDTH/32))),
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.C_USE_MEMORY (0),
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.C_DEPTH (C_PIPELINE_INPUT?1:0)
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/*AUTOINSTPARAM*/)
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input_register
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(
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// Outputs
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.WR_DATA_READY (WR_TX_DATA_READY),
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.RD_DATA ({wWrTxData,wWrTxDataStartFlag,wWrTxDataStartOffset,wWrTxDataEndFlag,wWrTxDataEndOffset}),
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.RD_DATA_VALID (wWrTxDataValid),
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// Inputs
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.WR_DATA ({WR_TX_DATA,WR_TX_DATA_START_FLAG,WR_TX_DATA_START_OFFSET,
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WR_TX_DATA_END_FLAG,WR_TX_DATA_END_OFFSET}),
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.WR_DATA_VALID (WR_TX_DATA_VALID),
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.RD_DATA_READY (wWrTxDataReady),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN));
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// The pipeline carries the data bus and SOF/EOF.
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pipeline
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#(// Parameters
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.C_WIDTH (C_DATA_WIDTH + 2*C_MASK_WIDTH + 1),
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.C_USE_MEMORY (0),
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.C_DEPTH ((C_PIPELINE_OUTPUT > 1) ? 1 : 0)
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/*AUTOINSTPARAM*/)
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output_register
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(
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// Outputs
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.WR_DATA_READY (wRdTxDataReady),
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.RD_DATA ({RD_TX_DATA,RD_TX_DATA_START_FLAG,
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RD_TX_DATA_END_FLAGS,RD_TX_DATA_WORD_VALID}),
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.RD_DATA_VALID (RD_TX_DATA_VALID),
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// Inputs
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.WR_DATA ({wRdTxData,wRdTxDataStartFlag,
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wRdTxDataEndFlags,wRdTxDataWordValid}),
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.WR_DATA_VALID (wRdTxDataValid),
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.RD_DATA_READY (RD_TX_DATA_READY),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN));
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offset_to_mask
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#(
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.C_MASK_SWAP (0),
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/*AUTOINSTPARAM*/
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// Parameters
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.C_MASK_WIDTH (C_MASK_WIDTH))
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eof_convert
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(
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// Outputs
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.MASK (wWrTxEndFlagMask),
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// Inputs
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.OFFSET_ENABLE (wWrTxDataEndFlag),
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.OFFSET (wWrTxDataEndOffset)
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/*AUTOINST*/);
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rotate
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#(
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// Parameters
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.C_DIRECTION ("RIGHT"),
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.C_WIDTH (C_DATA_WIDTH/32)
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/*AUTOINSTPARAM*/)
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em_rotate_inst
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(
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// Outputs
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.RD_DATA (wRdTxEndFlagMask),
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// Inputs
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.WR_DATA (wWrTxEndFlagMask),
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.WR_SHIFTAMT (rStartOffset[clog2s(C_DATA_WIDTH/32)-1:0])
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/*AUTOINST*/);
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// Determine the 1-hot dword end flag
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offset_flag_to_one_hot
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#(
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.C_WIDTH (C_DATA_WIDTH/32)
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/*AUTOINSTPARAM*/)
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ef_onehot_inst
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(
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// Outputs
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.RD_ONE_HOT (wWrTxDataEndFlags),
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// Inputs
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.WR_OFFSET (wWrTxDataEndOffset[clog2s(C_DATA_WIDTH/32)-1:0]),
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.WR_FLAG (wWrTxDataEndFlag)
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/*AUTOINST*/);
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rotate
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#(
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// Parameters
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.C_DIRECTION ("RIGHT"),
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.C_WIDTH (C_DATA_WIDTH/32)
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/*AUTOINSTPARAM*/)
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ef_rotate_inst
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(
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// Outputs
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.RD_DATA (wRdTxDataEndFlags),
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// Inputs
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.WR_DATA (wWrTxDataEndFlags),
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.WR_SHIFTAMT (rStartOffset[clog2s(C_DATA_WIDTH/32)-1:0])
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/*AUTOINST*/);
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generate
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for (i = 0; i < C_NUM_MUXES; i = i + 1) begin : gen_rotates
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rotate
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#(
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// Parameters
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.C_DIRECTION ("LEFT"),
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.C_WIDTH ((C_DATA_WIDTH/32))
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/*AUTOINSTPARAM*/)
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select_rotate_inst_
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(
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// Outputs
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.RD_DATA (wSelectRotated[i]),
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// Inputs
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.WR_DATA (wSelectDefault[i]),
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.WR_SHIFTAMT (WR_TX_DATA_START_OFFSET[C_ROTATE_BITS-1:0])
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/*AUTOINST*/);
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end
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endgenerate
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generate
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for (i = 0; i < C_DATA_WIDTH/32; i = i + 1) begin : gen_multiplexers
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one_hot_mux
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#(
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.C_DATA_WIDTH (32),
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/*AUTOINSTPARAM*/
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// Parameters
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.C_SELECT_WIDTH (C_SELECT_WIDTH),
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.C_AGGREGATE_WIDTH (C_AGGREGATE_WIDTH))
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mux_inst_
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(
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// Inputs
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.ONE_HOT_SELECT (rMuxSelect[i]),
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// Outputs
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.ONE_HOT_OUTPUT (wRdTxData[32*i +: 32]),
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.ONE_HOT_INPUTS (wWrTxData)
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/*AUTOINST*/);
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end
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endgenerate
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endmodule
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// Local Variables:
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// verilog-library-directories:("." "../../../common/" "../../common/")
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// End:
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