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riffa/fpga/xilinx/vc709
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Dustin Richmond c420b76c16 Finishing reset logic and testing/implementing across a wide swath of boards. 
Changes are mostly in the RX logic, where RST_IN was still used, though some new
logic (reset_extender) was added to riffa.v. Updated projects for: VC709, VC707,
ZC706 (partial), NetFPGA, ADM-7V3, ML605 (Still not working), AC701 (Untested)
and KC705 (Untested)
2015-08-12 16:16:27 -07:00
..
VC709_Gen1x8If64
Finishing reset logic and testing/implementing across a wide swath of boards.
2015-08-12 16:16:27 -07:00
VC709_Gen2x8If128
Finishing reset logic and testing/implementing across a wide swath of boards.
2015-08-12 16:16:27 -07:00
VC709_Gen3x4If128
Finishing reset logic and testing/implementing across a wide swath of boards.
2015-08-12 16:16:27 -07:00
riffa_wrapper_vc709.v
Finishing reset logic and testing/implementing across a wide swath of boards.
2015-08-12 16:16:27 -07:00