mirror of
https://github.com/KastnerRG/riffa.git
synced 2025-01-30 23:02:54 +08:00
c420b76c16
Changes are mostly in the RX logic, where RST_IN was still used, though some new logic (reset_extender) was added to riffa.v. Updated projects for: VC709, VC707, ZC706 (partial), NetFPGA, ADM-7V3, ML605 (Still not working), AC701 (Untested) and KC705 (Untested)
746 lines
38 KiB
Verilog
746 lines
38 KiB
Verilog
// ----------------------------------------------------------------------
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// Copyright (c) 2015, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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`include "trellis.vh"
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`include "riffa.vh"
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`timescale 1ns/1ns
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module riffa
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#(parameter C_PCI_DATA_WIDTH = 128,
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parameter C_NUM_CHNL = 12,
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parameter C_MAX_READ_REQ_BYTES = 512, // Max size of read requests (in bytes)
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parameter C_TAG_WIDTH = 5, // Number of outstanding requests
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parameter C_VENDOR = "ALTERA",
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parameter C_FPGA_NAME = "FPGA", // TODO: Give each channel a unique name
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parameter C_FPGA_ID = 0,// A value from 0 to 255 uniquely identifying this RIFFA design
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parameter C_DEPTH_PACKETS = 10
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)
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(input CLK,
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input RST_BUS,
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output RST_OUT,
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input DONE_TXC_RST,
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input DONE_TXR_RST,
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// Interface: RXC Engine
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input [C_PCI_DATA_WIDTH-1:0] RXC_DATA,
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input RXC_DATA_VALID,
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input [(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_WORD_ENABLE,
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input RXC_DATA_START_FLAG,
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input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_START_OFFSET,
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input RXC_DATA_END_FLAG,
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input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_END_OFFSET,
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input [`SIG_LBE_W-1:0] RXC_META_LDWBE,
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input [`SIG_FBE_W-1:0] RXC_META_FDWBE,
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input [`SIG_TAG_W-1:0] RXC_META_TAG,
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input [`SIG_LOWADDR_W-1:0] RXC_META_ADDR,
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input [`SIG_TYPE_W-1:0] RXC_META_TYPE,
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input [`SIG_LEN_W-1:0] RXC_META_LENGTH,
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input [`SIG_BYTECNT_W-1:0] RXC_META_BYTES_REMAINING,
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input [`SIG_CPLID_W-1:0] RXC_META_COMPLETER_ID,
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input RXC_META_EP,
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// Interface: RXR Engine
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input [C_PCI_DATA_WIDTH-1:0] RXR_DATA,
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input RXR_DATA_VALID,
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input [(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_WORD_ENABLE,
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input RXR_DATA_START_FLAG,
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input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET,
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input RXR_DATA_END_FLAG,
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input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET,
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input [`SIG_FBE_W-1:0] RXR_META_FDWBE,
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input [`SIG_LBE_W-1:0] RXR_META_LDWBE,
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input [`SIG_TC_W-1:0] RXR_META_TC,
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input [`SIG_ATTR_W-1:0] RXR_META_ATTR,
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input [`SIG_TAG_W-1:0] RXR_META_TAG,
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input [`SIG_TYPE_W-1:0] RXR_META_TYPE,
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input [`SIG_ADDR_W-1:0] RXR_META_ADDR,
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input [`SIG_BARDECODE_W-1:0] RXR_META_BAR_DECODED,
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input [`SIG_REQID_W-1:0] RXR_META_REQUESTER_ID,
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input [`SIG_LEN_W-1:0] RXR_META_LENGTH,
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input RXR_META_EP,
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// Interface: TXC Engine
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output [C_PCI_DATA_WIDTH-1:0] TXC_DATA,
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output TXC_DATA_VALID,
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output TXC_DATA_START_FLAG,
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output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_START_OFFSET,
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output TXC_DATA_END_FLAG,
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output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_END_OFFSET,
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input TXC_DATA_READY,
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output TXC_META_VALID,
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output [`SIG_FBE_W-1:0] TXC_META_FDWBE,
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output [`SIG_LBE_W-1:0] TXC_META_LDWBE,
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output [`SIG_LOWADDR_W-1:0] TXC_META_ADDR,
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output [`SIG_TYPE_W-1:0] TXC_META_TYPE,
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output [`SIG_LEN_W-1:0] TXC_META_LENGTH,
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output [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT,
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output [`SIG_TAG_W-1:0] TXC_META_TAG,
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output [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID,
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output [`SIG_TC_W-1:0] TXC_META_TC,
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output [`SIG_ATTR_W-1:0] TXC_META_ATTR,
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output TXC_META_EP,
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input TXC_META_READY,
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input TXC_SENT,
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// Interface: TXR Engine
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output TXR_DATA_VALID,
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output [C_PCI_DATA_WIDTH-1:0] TXR_DATA,
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output TXR_DATA_START_FLAG,
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output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
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output TXR_DATA_END_FLAG,
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output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
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input TXR_DATA_READY,
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output TXR_META_VALID,
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output [`SIG_FBE_W-1:0] TXR_META_FDWBE,
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output [`SIG_LBE_W-1:0] TXR_META_LDWBE,
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output [`SIG_ADDR_W-1:0] TXR_META_ADDR,
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output [`SIG_LEN_W-1:0] TXR_META_LENGTH,
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output [`SIG_TAG_W-1:0] TXR_META_TAG,
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output [`SIG_TC_W-1:0] TXR_META_TC,
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output [`SIG_ATTR_W-1:0] TXR_META_ATTR,
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output [`SIG_TYPE_W-1:0] TXR_META_TYPE,
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output TXR_META_EP,
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input TXR_META_READY,
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input TXR_SENT,
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// Interface: Configuration
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input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
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input CONFIG_BUS_MASTER_ENABLE,
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input [`SIG_LINKWIDTH_W-1:0] CONFIG_LINK_WIDTH,
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input [`SIG_LINKRATE_W-1:0] CONFIG_LINK_RATE,
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input [`SIG_MAXREAD_W-1:0] CONFIG_MAX_READ_REQUEST_SIZE,
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input [`SIG_MAXPAYLOAD_W-1:0] CONFIG_MAX_PAYLOAD_SIZE,
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input [`SIG_FC_CPLD_W-1:0] CONFIG_MAX_CPL_DATA, // Receive credit limit for data
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input [`SIG_FC_CPLH_W-1:0] CONFIG_MAX_CPL_HDR, // Receive credit limit for headers
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input CONFIG_INTERRUPT_MSIENABLE,
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input CONFIG_CPL_BOUNDARY_SEL,
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// Interrupt Request
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input INTR_MSI_RDY, // High when interrupt is able to be sent
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output INTR_MSI_REQUEST, // High to request interrupt, when both INTR_MSI_RDY and INTR_MSI_RE
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input [C_NUM_CHNL-1:0] CHNL_RX_CLK,
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output [C_NUM_CHNL-1:0] CHNL_RX,
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input [C_NUM_CHNL-1:0] CHNL_RX_ACK,
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output [C_NUM_CHNL-1:0] CHNL_RX_LAST,
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output [(C_NUM_CHNL*32)-1:0] CHNL_RX_LEN,
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output [(C_NUM_CHNL*31)-1:0] CHNL_RX_OFF,
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output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_RX_DATA,
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output [C_NUM_CHNL-1:0] CHNL_RX_DATA_VALID,
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input [C_NUM_CHNL-1:0] CHNL_RX_DATA_REN,
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input [C_NUM_CHNL-1:0] CHNL_TX_CLK,
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input [C_NUM_CHNL-1:0] CHNL_TX,
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output [C_NUM_CHNL-1:0] CHNL_TX_ACK,
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input [C_NUM_CHNL-1:0] CHNL_TX_LAST,
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input [(C_NUM_CHNL*32)-1:0] CHNL_TX_LEN,
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input [(C_NUM_CHNL*31)-1:0] CHNL_TX_OFF,
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input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA,
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input [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID,
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output [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN
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);
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localparam C_MAX_READ_REQ = clog2s(C_MAX_READ_REQ_BYTES)-7; // Max read: 000=128B; 001=256B; 010=512B; 011=1024B; 100=2048B; 101=4096B
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localparam C_NUM_CHNL_WIDTH = clog2s(C_NUM_CHNL);
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localparam C_PCI_DATA_WORD_WIDTH = clog2s((C_PCI_DATA_WIDTH/32)+1);
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localparam C_NUM_VECTORS = 2;
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localparam C_VECTOR_WIDTH = 32;
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// Interface: Reorder Buffer Output
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wire [(C_NUM_CHNL*C_PCI_DATA_WORD_WIDTH)-1:0] wRxEngMainDataEn; // Start offset and end offset
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wire [C_PCI_DATA_WIDTH-1:0] wRxEngData;
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wire [C_NUM_CHNL-1:0] wRxEngMainDone;
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wire [C_NUM_CHNL-1:0] wRxEngMainErr;
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// Interface: Reorder Buffer to SG RX engines
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wire [(C_NUM_CHNL*C_PCI_DATA_WORD_WIDTH)-1:0] wRxEngSgRxDataEn;
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wire [C_NUM_CHNL-1:0] wRxEngSgRxDone;
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wire [C_NUM_CHNL-1:0] wRxEngSgRxErr;
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// Interface: Reorder Buffer to SG TX engines
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wire [(C_NUM_CHNL*C_PCI_DATA_WORD_WIDTH)-1:0] wRxEngSgTxDataEn;
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wire [C_NUM_CHNL-1:0] wRxEngSgTxDone;
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wire [C_NUM_CHNL-1:0] wRxEngSgTxErr;
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// Interface: Channel TX Write
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wire [C_NUM_CHNL-1:0] wTxEngWrReq;
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wire [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] wTxEngWrAddr;
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wire [(C_NUM_CHNL*`SIG_LEN_W)-1:0] wTxEngWrLen;
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wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] wTxEngWrData;
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wire [C_NUM_CHNL-1:0] wTxEngWrDataRen;
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wire [C_NUM_CHNL-1:0] wTxEngWrAck;
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wire [C_NUM_CHNL-1:0] wTxEngWrSent;
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// Interface: Channel TX Read
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wire [C_NUM_CHNL-1:0] wTxEngRdReq;
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wire [(C_NUM_CHNL*2)-1:0] wTxEngRdSgChnl;
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wire [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] wTxEngRdAddr;
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wire [(C_NUM_CHNL*`SIG_LEN_W)-1:0] wTxEngRdLen;
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wire [C_NUM_CHNL-1:0] wTxEngRdAck;
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// Interface: Channel Interrupts
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wire [C_NUM_CHNL-1:0] wChnlSgRxBufRecvd;
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wire [C_NUM_CHNL-1:0] wChnlRxDone;
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wire [C_NUM_CHNL-1:0] wChnlTxRequest;
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wire [C_NUM_CHNL-1:0] wChnlTxDone;
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wire [C_NUM_CHNL-1:0] wChnlSgTxBufRecvd;
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wire wInternalTagValid;
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wire [5:0] wInternalTag;
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wire wExternalTagValid;
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wire [C_TAG_WIDTH-1:0] wExternalTag;
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// Interface: Channel - PIO Read
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wire [C_NUM_CHNL-1:0] wChnlTxLenReady;
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wire [(`SIG_TXRLEN_W*C_NUM_CHNL)-1:0] wChnlTxReqLen;
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wire [C_NUM_CHNL-1:0] wChnlTxOfflastReady;
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wire [(`SIG_OFFLAST_W*C_NUM_CHNL)-1:0] wChnlTxOfflast;
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wire wCoreSettingsReady;
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wire [`SIG_CORESETTINGS_W-1:0] wCoreSettings;
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wire [C_NUM_VECTORS-1:0] wIntrVectorReady;
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wire [C_NUM_VECTORS*C_VECTOR_WIDTH-1:0] wIntrVector;
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wire [C_NUM_CHNL-1:0] wChnlTxDoneReady;
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wire [(`SIG_TXDONELEN_W*C_NUM_CHNL)-1:0] wChnlTxDoneLen;
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wire [C_NUM_CHNL-1:0] wChnlRxDoneReady;
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wire [(`SIG_RXDONELEN_W*C_NUM_CHNL)-1:0] wChnlRxDoneLen;
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wire wChnlNameReady;
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// Interface: Channel - PIO Write
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wire [31:0] wChnlReqData;
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wire [C_NUM_CHNL-1:0] wChnlSgRxLenValid;
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wire [C_NUM_CHNL-1:0] wChnlSgRxAddrLoValid;
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wire [C_NUM_CHNL-1:0] wChnlSgRxAddrHiValid;
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wire [C_NUM_CHNL-1:0] wChnlSgTxLenValid;
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wire [C_NUM_CHNL-1:0] wChnlSgTxAddrLoValid;
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wire [C_NUM_CHNL-1:0] wChnlSgTxAddrHiValid;
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wire [C_NUM_CHNL-1:0] wChnlRxLenValid;
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wire [C_NUM_CHNL-1:0] wChnlRxOfflastValid;
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// Interface: TXC Engine
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wire [C_PCI_DATA_WIDTH-1:0] _wTxcData, wTxcData;
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wire _wTxcDataValid, wTxcDataValid;
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wire _wTxcDataStartFlag, wTxcDataStartFlag;
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wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] _wTxcDataStartOffset, wTxcDataStartOffset;
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wire _wTxcDataEndFlag, wTxcDataEndFlag;
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wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] _wTxcDataEndOffset, wTxcDataEndOffset;
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wire _wTxcDataReady, wTxcDataReady;
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wire _wTxcMetaValid, wTxcMetaValid;
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wire [`SIG_FBE_W-1:0] _wTxcMetaFdwbe, wTxcMetaFdwbe;
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wire [`SIG_LBE_W-1:0] _wTxcMetaLdwbe, wTxcMetaLdwbe;
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wire [`SIG_LOWADDR_W-1:0] _wTxcMetaAddr, wTxcMetaAddr;
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wire [`SIG_TYPE_W-1:0] _wTxcMetaType, wTxcMetaType;
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wire [`SIG_LEN_W-1:0] _wTxcMetaLength, wTxcMetaLength;
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wire [`SIG_BYTECNT_W-1:0] _wTxcMetaByteCount, wTxcMetaByteCount;
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wire [`SIG_TAG_W-1:0] _wTxcMetaTag, wTxcMetaTag;
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wire [`SIG_REQID_W-1:0] _wTxcMetaRequesterId, wTxcMetaRequesterId;
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wire [`SIG_TC_W-1:0] _wTxcMetaTc, wTxcMetaTc;
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wire [`SIG_ATTR_W-1:0] _wTxcMetaAttr, wTxcMetaAttr;
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wire _wTxcMetaEp, wTxcMetaEp;
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wire _wTxcMetaReady, wTxcMetaReady;
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wire wRxBufSpaceAvail;
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wire wTxEngRdReqSent;
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wire wRxEngRdComplete;
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wire [31:0] wCPciDataWidth;
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reg [31:0] wCFpgaId;
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reg [4:0] rWideRst;
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reg rRst;
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genvar i;
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assign wRxEngRdComplete = RXC_DATA_END_FLAG & RXC_DATA_VALID &
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(RXC_META_LENGTH >= RXC_META_BYTES_REMAINING[`SIG_BYTECNT_W-1:2]);// TODO: Retime (if possible)
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assign wCoreSettings = {1'd0, wCFpgaId, wCPciDataWidth[8:5],
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CONFIG_MAX_PAYLOAD_SIZE, CONFIG_MAX_READ_REQUEST_SIZE,
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CONFIG_LINK_RATE[1:0], CONFIG_LINK_WIDTH, CONFIG_BUS_MASTER_ENABLE,
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C_NUM_CHNL[3:0]};
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// Interface: TXC Engine
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assign TXC_DATA = wTxcData;
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assign TXC_DATA_START_FLAG = wTxcDataStartFlag;
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assign TXC_DATA_START_OFFSET = wTxcDataStartOffset;
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assign TXC_DATA_END_FLAG = wTxcDataEndFlag;
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assign TXC_DATA_END_OFFSET = wTxcDataEndOffset;
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assign TXC_DATA_VALID = wTxcDataValid & ~wPendingRst & DONE_TXC_RST;
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assign wTxcDataReady = TXC_DATA_READY & ~wPendingRst & DONE_TXC_RST;
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assign TXC_META_FDWBE = wTxcMetaFdwbe;
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assign TXC_META_LDWBE = wTxcMetaLdwbe;
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assign TXC_META_ADDR = wTxcMetaAddr;
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assign TXC_META_TYPE = wTxcMetaType;
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assign TXC_META_LENGTH = wTxcMetaLength;
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assign TXC_META_BYTE_COUNT = wTxcMetaByteCount;
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assign TXC_META_TAG = wTxcMetaTag;
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assign TXC_META_REQUESTER_ID = wTxcMetaRequesterId;
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assign TXC_META_TC = wTxcMetaTc;
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assign TXC_META_ATTR = wTxcMetaAttr;
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assign TXC_META_EP = wTxcMetaEp;
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assign TXC_META_VALID = wTxcMetaValid & ~wPendingRst & DONE_TXC_RST;
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assign wTxcMetaReady = TXC_META_READY & ~wPendingRst & DONE_TXC_RST;
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/* Workaround for a bug reported by the NetFPGA group, where the parameter
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C_PCI_DATA_WIDTH cannot be directly assigned to a wire. */
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generate
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if(C_PCI_DATA_WIDTH == 32) begin
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assign wCPciDataWidth = 32;
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end else if (C_PCI_DATA_WIDTH == 64) begin
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assign wCPciDataWidth = 64;
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end else if (C_PCI_DATA_WIDTH == 128) begin
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assign wCPciDataWidth = 128;
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end else if (C_PCI_DATA_WIDTH == 256) begin
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assign wCPciDataWidth = 256;
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end
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always @(*) begin
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wCFpgaId = 0;
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if((C_FPGA_ID & 128) != 0) begin
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wCFpgaId[7] = 1;
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end else if ((C_FPGA_ID & 64) != 1) begin
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wCFpgaId[6] = 1;
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end else if ((C_FPGA_ID & 32) != 1) begin
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wCFpgaId[5] = 1;
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end else if ((C_FPGA_ID & 16) != 1) begin
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wCFpgaId[4] = 1;
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end else if ((C_FPGA_ID & 8) != 1) begin
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wCFpgaId[3] = 1;
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end else if ((C_FPGA_ID & 4) != 1) begin
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wCFpgaId[2] = 1;
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end else if ((C_FPGA_ID & 2) != 1) begin
|
|
wCFpgaId[1] = 1;
|
|
end else if ((C_FPGA_ID & 1) != 1) begin
|
|
wCFpgaId[0] = 1;
|
|
end
|
|
end
|
|
endgenerate
|
|
|
|
/* The purpose of these two hold modules is to safely reset the TX path and
|
|
still respond to the core status request (which causes a RIFFA reset). We
|
|
could wait until after the completion has been transmitted, but we have no
|
|
guarantee that the TX path is operating correctly until after we reset */
|
|
|
|
pipeline
|
|
#(// Parameters
|
|
.C_DEPTH (1),
|
|
|
|
.C_WIDTH (2 * `SIG_FBE_W + `SIG_LOWADDR_W +
|
|
`SIG_TYPE_W + `SIG_LEN_W +
|
|
`SIG_BYTECNT_W + `SIG_TAG_W +
|
|
`SIG_REQID_W + `SIG_TC_W +
|
|
`SIG_ATTR_W + 1),
|
|
.C_USE_MEMORY (0)
|
|
/*AUTOINSTPARAM*/)
|
|
txc_meta_hold
|
|
(// Outputs
|
|
.WR_DATA_READY (_wTxcMetaReady), // NC
|
|
.RD_DATA ({wTxcMetaFdwbe, wTxcMetaLdwbe,
|
|
wTxcMetaAddr, wTxcMetaType,
|
|
wTxcMetaLength,
|
|
wTxcMetaByteCount, wTxcMetaTag,
|
|
wTxcMetaRequesterId, wTxcMetaTc,
|
|
wTxcMetaAttr, wTxcMetaEp}),
|
|
.RD_DATA_VALID (wTxcMetaValid),
|
|
// Inputs
|
|
.WR_DATA ({_wTxcMetaFdwbe, _wTxcMetaLdwbe,
|
|
_wTxcMetaAddr, _wTxcMetaType,
|
|
_wTxcMetaLength,
|
|
_wTxcMetaByteCount, _wTxcMetaTag,
|
|
_wTxcMetaRequesterId, _wTxcMetaTc,
|
|
_wTxcMetaAttr, _wTxcMetaEp}),
|
|
.WR_DATA_VALID (_wTxcMetaValid),
|
|
.RD_DATA_READY (wTxcMetaReady),
|
|
.RST_IN (RST_BUS),
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.CLK (CLK));
|
|
|
|
pipeline
|
|
#(// Parameters
|
|
.C_DEPTH (1),
|
|
.C_WIDTH (C_PCI_DATA_WIDTH +
|
|
2 * (clog2s(C_PCI_DATA_WIDTH/32) + 1)),
|
|
.C_USE_MEMORY (0)
|
|
/*AUTOINSTPARAM*/)
|
|
txc_data_hold
|
|
(// Outputs
|
|
.WR_DATA_READY (_wTxcDataReady), // NC
|
|
.RD_DATA ({wTxcData, wTxcDataStartFlag,
|
|
wTxcDataStartOffset, wTxcDataEndFlag,
|
|
wTxcDataEndOffset}),
|
|
.RD_DATA_VALID (wTxcDataValid),
|
|
// Inputs
|
|
.WR_DATA ({_wTxcData, _wTxcDataStartFlag,
|
|
_wTxcDataStartOffset, _wTxcDataEndFlag,
|
|
_wTxcDataEndOffset}),
|
|
.WR_DATA_VALID (_wTxcDataValid),
|
|
.RD_DATA_READY (wTxcDataReady),
|
|
.RST_IN (RST_BUS),
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.CLK (CLK));
|
|
|
|
reset_extender
|
|
#(.C_RST_COUNT (8)
|
|
/*AUTOINSTPARAM*/)
|
|
reset_extender_inst
|
|
(// Outputs
|
|
.PENDING_RST (wPendingRst),
|
|
// Inputs
|
|
.RST_IN (RST_BUS | wCoreSettingsReady),
|
|
/*AUTOINST*/
|
|
// Outputs
|
|
.RST_OUT (RST_OUT),
|
|
// Inputs
|
|
.CLK (CLK));
|
|
|
|
reorder_queue
|
|
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),
|
|
.C_NUM_CHNL(C_NUM_CHNL),
|
|
.C_MAX_READ_REQ_BYTES(C_MAX_READ_REQ_BYTES),
|
|
.C_TAG_WIDTH(C_TAG_WIDTH))
|
|
reorderQueue
|
|
(.RST (RST_OUT),
|
|
.VALID (RXC_DATA_VALID),
|
|
.DATA_START_FLAG (RXC_DATA_START_FLAG),
|
|
.DATA_START_OFFSET (RXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
|
|
.DATA_END_FLAG (RXC_DATA_END_FLAG),
|
|
.DATA_END_OFFSET (RXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
|
|
.DATA (RXC_DATA),
|
|
.DATA_EN (RXC_DATA_WORD_ENABLE),
|
|
.DONE (wRxEngRdComplete),
|
|
.ERR (RXC_META_EP),
|
|
.TAG (RXC_META_TAG[C_TAG_WIDTH-1:0]),
|
|
.INT_TAG (wInternalTag),
|
|
.INT_TAG_VALID (wInternalTagValid),
|
|
.EXT_TAG (wExternalTag),
|
|
.EXT_TAG_VALID (wExternalTagValid),
|
|
.ENG_DATA (wRxEngData),
|
|
.MAIN_DATA_EN (wRxEngMainDataEn),
|
|
.MAIN_DONE (wRxEngMainDone),
|
|
.MAIN_ERR (wRxEngMainErr),
|
|
.SG_RX_DATA_EN (wRxEngSgRxDataEn),
|
|
.SG_RX_DONE (wRxEngSgRxDone),
|
|
.SG_RX_ERR (wRxEngSgRxErr),
|
|
.SG_TX_DATA_EN (wRxEngSgTxDataEn),
|
|
.SG_TX_DONE (wRxEngSgTxDone),
|
|
.SG_TX_ERR (wRxEngSgTxErr),
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.CLK (CLK));
|
|
|
|
registers
|
|
#(// Parameters
|
|
.C_PIPELINE_OUTPUT (1),
|
|
.C_PIPELINE_INPUT (1),
|
|
/*AUTOINSTPARAM*/
|
|
// Parameters
|
|
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
|
|
.C_NUM_CHNL (C_NUM_CHNL),
|
|
.C_MAX_READ_REQ_BYTES (C_MAX_READ_REQ_BYTES),
|
|
.C_VENDOR (C_VENDOR),
|
|
.C_NUM_VECTORS (C_NUM_VECTORS),
|
|
.C_VECTOR_WIDTH (C_VECTOR_WIDTH),
|
|
.C_FPGA_NAME (C_FPGA_NAME))
|
|
reg_inst
|
|
(// Outputs
|
|
// Write Interfaces
|
|
.CHNL_REQ_DATA (wChnlReqData[31:0]),
|
|
.CHNL_SGRX_LEN_VALID (wChnlSgRxLenValid),
|
|
.CHNL_SGRX_ADDRLO_VALID (wChnlSgRxAddrLoValid),
|
|
.CHNL_SGRX_ADDRHI_VALID (wChnlSgRxAddrHiValid),
|
|
.CHNL_SGTX_LEN_VALID (wChnlSgTxLenValid),
|
|
.CHNL_SGTX_ADDRLO_VALID (wChnlSgTxAddrLoValid),
|
|
.CHNL_SGTX_ADDRHI_VALID (wChnlSgTxAddrHiValid),
|
|
.CHNL_RX_LEN_VALID (wChnlRxLenValid),
|
|
.CHNL_RX_OFFLAST_VALID (wChnlRxOfflastValid),
|
|
// Read Interfaces
|
|
.CHNL_TX_LEN_READY (wChnlTxLenReady),
|
|
.CHNL_TX_OFFLAST_READY (wChnlTxOfflastReady),
|
|
.CORE_SETTINGS_READY (wCoreSettingsReady),
|
|
.INTR_VECTOR_READY (wIntrVectorReady),
|
|
.CHNL_TX_DONE_READY (wChnlTxDoneReady),
|
|
.CHNL_RX_DONE_READY (wChnlRxDoneReady),
|
|
.CHNL_NAME_READY (wChnlNameReady), // TODO: Could do this on a per-channel basis
|
|
// TXC Engine Interface
|
|
.TXC_DATA_VALID (_wTxcDataValid),
|
|
.TXC_DATA (_wTxcData[C_PCI_DATA_WIDTH-1:0]),
|
|
.TXC_DATA_START_FLAG (_wTxcDataStartFlag),
|
|
.TXC_DATA_START_OFFSET (_wTxcDataStartOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
|
|
.TXC_DATA_END_FLAG (_wTxcDataEndFlag),
|
|
.TXC_DATA_END_OFFSET (_wTxcDataEndOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
|
|
.TXC_META_VALID (_wTxcMetaValid),
|
|
.TXC_META_FDWBE (_wTxcMetaFdwbe[`SIG_FBE_W-1:0]),
|
|
.TXC_META_LDWBE (_wTxcMetaLdwbe[`SIG_LBE_W-1:0]),
|
|
.TXC_META_ADDR (_wTxcMetaAddr[`SIG_LOWADDR_W-1:0]),
|
|
.TXC_META_TYPE (_wTxcMetaType[`SIG_TYPE_W-1:0]),
|
|
.TXC_META_LENGTH (_wTxcMetaLength[`SIG_LEN_W-1:0]),
|
|
.TXC_META_BYTE_COUNT (_wTxcMetaByteCount[`SIG_BYTECNT_W-1:0]),
|
|
.TXC_META_TAG (_wTxcMetaTag[`SIG_TAG_W-1:0]),
|
|
.TXC_META_REQUESTER_ID (_wTxcMetaRequesterId[`SIG_REQID_W-1:0]),
|
|
.TXC_META_TC (_wTxcMetaTc[`SIG_TC_W-1:0]),
|
|
.TXC_META_ATTR (_wTxcMetaAttr[`SIG_ATTR_W-1:0]),
|
|
.TXC_META_EP (_wTxcMetaEp),
|
|
// Inputs
|
|
// Read Data
|
|
.CORE_SETTINGS (wCoreSettings),
|
|
.CHNL_TX_REQLEN (wChnlTxReqLen),
|
|
.CHNL_TX_OFFLAST (wChnlTxOfflast),
|
|
.CHNL_TX_DONELEN (wChnlTxDoneLen),
|
|
.CHNL_RX_DONELEN (wChnlRxDoneLen),
|
|
.INTR_VECTOR (wIntrVector),
|
|
.RST_IN (RST_OUT),
|
|
.TXC_DATA_READY (_wTxcDataReady),
|
|
.TXC_META_READY (_wTxcMetaReady),
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.CLK (CLK),
|
|
.RXR_DATA (RXR_DATA[C_PCI_DATA_WIDTH-1:0]),
|
|
.RXR_DATA_VALID (RXR_DATA_VALID),
|
|
.RXR_DATA_START_FLAG (RXR_DATA_START_FLAG),
|
|
.RXR_DATA_START_OFFSET (RXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
|
|
.RXR_META_FDWBE (RXR_META_FDWBE[`SIG_FBE_W-1:0]),
|
|
.RXR_DATA_END_FLAG (RXR_DATA_END_FLAG),
|
|
.RXR_DATA_END_OFFSET (RXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
|
|
.RXR_META_LDWBE (RXR_META_LDWBE[`SIG_LBE_W-1:0]),
|
|
.RXR_META_TC (RXR_META_TC[`SIG_TC_W-1:0]),
|
|
.RXR_META_ATTR (RXR_META_ATTR[`SIG_ATTR_W-1:0]),
|
|
.RXR_META_TAG (RXR_META_TAG[`SIG_TAG_W-1:0]),
|
|
.RXR_META_TYPE (RXR_META_TYPE[`SIG_TYPE_W-1:0]),
|
|
.RXR_META_ADDR (RXR_META_ADDR[`SIG_ADDR_W-1:0]),
|
|
.RXR_META_BAR_DECODED (RXR_META_BAR_DECODED[`SIG_BARDECODE_W-1:0]),
|
|
.RXR_META_REQUESTER_ID (RXR_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
|
|
.RXR_META_LENGTH (RXR_META_LENGTH[`SIG_LEN_W-1:0]));
|
|
|
|
// Track receive buffer flow control credits (header & Data)
|
|
recv_credit_flow_ctrl rc_fc
|
|
(// Outputs
|
|
.RXBUF_SPACE_AVAIL (wRxBufSpaceAvail),
|
|
// Inputs
|
|
.RX_ENG_RD_DONE (wRxEngRdComplete),
|
|
.TX_ENG_RD_REQ_SENT (wTxEngRdReqSent),
|
|
.RST (RST_OUT),
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.CLK (CLK),
|
|
.CONFIG_MAX_READ_REQUEST_SIZE (CONFIG_MAX_READ_REQUEST_SIZE[2:0]),
|
|
.CONFIG_MAX_CPL_DATA (CONFIG_MAX_CPL_DATA[11:0]),
|
|
.CONFIG_MAX_CPL_HDR (CONFIG_MAX_CPL_HDR[7:0]),
|
|
.CONFIG_CPL_BOUNDARY_SEL (CONFIG_CPL_BOUNDARY_SEL));
|
|
// Connect the interrupt vector and controller.
|
|
interrupt
|
|
#(.C_NUM_CHNL (C_NUM_CHNL))
|
|
intr
|
|
(// Inputs
|
|
.RST (RST_OUT),
|
|
.RX_SG_BUF_RECVD (wChnlSgRxBufRecvd),
|
|
.RX_TXN_DONE (wChnlRxDone),
|
|
.TX_TXN (wChnlTxRequest),
|
|
.TX_SG_BUF_RECVD (wChnlSgTxBufRecvd),
|
|
.TX_TXN_DONE (wChnlTxDone),
|
|
.VECT_0_RST (wIntrVectorReady[0]),
|
|
.VECT_1_RST (wIntrVectorReady[1]),
|
|
.VECT_RST (_wTxcData[31:0]),
|
|
.VECT_0 (wIntrVector[31:0]),
|
|
.VECT_1 (wIntrVector[63:32]),
|
|
.INTR_LEGACY_CLR (1'd0),
|
|
/*AUTOINST*/
|
|
// Outputs
|
|
.INTR_MSI_REQUEST (INTR_MSI_REQUEST),
|
|
// Inputs
|
|
.CLK (CLK),
|
|
.CONFIG_INTERRUPT_MSIENABLE (CONFIG_INTERRUPT_MSIENABLE),
|
|
.INTR_MSI_RDY (INTR_MSI_RDY));
|
|
|
|
|
|
tx_multiplexer
|
|
#(/*AUTOINSTPARAM*/
|
|
// Parameters
|
|
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
|
|
.C_NUM_CHNL (C_NUM_CHNL),
|
|
.C_TAG_WIDTH (C_TAG_WIDTH),
|
|
.C_VENDOR (C_VENDOR),
|
|
.C_DEPTH_PACKETS (C_DEPTH_PACKETS))
|
|
tx_mux_inst
|
|
(
|
|
// Outputs
|
|
.WR_DATA_REN (wTxEngWrDataRen[C_NUM_CHNL-1:0]),
|
|
.WR_ACK (wTxEngWrAck[C_NUM_CHNL-1:0]),
|
|
.RD_ACK (wTxEngRdAck[C_NUM_CHNL-1:0]),
|
|
.INT_TAG (wInternalTag[5:0]),
|
|
.INT_TAG_VALID (wInternalTagValid),
|
|
.TX_ENG_RD_REQ_SENT (wTxEngRdReqSent),
|
|
// Inputs
|
|
.RST_IN (RST_OUT),
|
|
.WR_REQ (wTxEngWrReq[C_NUM_CHNL-1:0]),
|
|
.WR_ADDR (wTxEngWrAddr[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
|
|
.WR_LEN (wTxEngWrLen[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
|
|
.WR_DATA (wTxEngWrData[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
|
|
.WR_SENT (wTxEngWrSent[C_NUM_CHNL-1:0]),
|
|
.RD_REQ (wTxEngRdReq[C_NUM_CHNL-1:0]),
|
|
.RD_SG_CHNL (wTxEngRdSgChnl[(C_NUM_CHNL*2)-1:0]),
|
|
.RD_ADDR (wTxEngRdAddr[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
|
|
.RD_LEN (wTxEngRdLen[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
|
|
.EXT_TAG (wExternalTag[C_TAG_WIDTH-1:0]),
|
|
.EXT_TAG_VALID (wExternalTagValid),
|
|
.RXBUF_SPACE_AVAIL (wRxBufSpaceAvail),
|
|
/*AUTOINST*/
|
|
// Outputs
|
|
.TXR_DATA_VALID (TXR_DATA_VALID),
|
|
.TXR_DATA (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
|
|
.TXR_DATA_START_FLAG (TXR_DATA_START_FLAG),
|
|
.TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
|
|
.TXR_DATA_END_FLAG (TXR_DATA_END_FLAG),
|
|
.TXR_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
|
|
.TXR_META_VALID (TXR_META_VALID),
|
|
.TXR_META_FDWBE (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
|
|
.TXR_META_LDWBE (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
|
|
.TXR_META_ADDR (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
|
|
.TXR_META_LENGTH (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
|
|
.TXR_META_TAG (TXR_META_TAG[`SIG_TAG_W-1:0]),
|
|
.TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]),
|
|
.TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
|
|
.TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
|
|
.TXR_META_EP (TXR_META_EP),
|
|
// Inputs
|
|
.CLK (CLK),
|
|
.TXR_DATA_READY (TXR_DATA_READY),
|
|
.TXR_META_READY (TXR_META_READY),
|
|
.TXR_SENT (TXR_SENT));
|
|
|
|
// Generate and link up the channels.
|
|
generate
|
|
for (i = 0; i < C_NUM_CHNL; i = i + 1) begin : channels
|
|
channel
|
|
#(
|
|
.C_DATA_WIDTH(C_PCI_DATA_WIDTH),
|
|
.C_MAX_READ_REQ(C_MAX_READ_REQ)
|
|
)
|
|
channel
|
|
(
|
|
.RST(RST_OUT),
|
|
.CLK(CLK),
|
|
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
|
|
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
|
|
|
|
.PIO_DATA(wChnlReqData),
|
|
.ENG_DATA(wRxEngData),
|
|
|
|
.SG_RX_BUF_RECVD(wChnlSgRxBufRecvd[i]),
|
|
.SG_TX_BUF_RECVD(wChnlSgTxBufRecvd[i]),
|
|
.TXN_TX(wChnlTxRequest[i]),
|
|
.TXN_TX_DONE(wChnlTxDone[i]),
|
|
.TXN_RX_DONE(wChnlRxDone[i]),
|
|
|
|
.SG_RX_BUF_LEN_VALID(wChnlSgRxLenValid[i]),
|
|
.SG_RX_BUF_ADDR_HI_VALID(wChnlSgRxAddrHiValid[i]),
|
|
.SG_RX_BUF_ADDR_LO_VALID(wChnlSgRxAddrLoValid[i]),
|
|
|
|
.SG_TX_BUF_LEN_VALID(wChnlSgTxLenValid[i]),
|
|
.SG_TX_BUF_ADDR_HI_VALID(wChnlSgTxAddrHiValid[i]),
|
|
.SG_TX_BUF_ADDR_LO_VALID(wChnlSgTxAddrLoValid[i]),
|
|
|
|
.TXN_RX_LEN_VALID(wChnlRxLenValid[i]),
|
|
.TXN_RX_OFF_LAST_VALID(wChnlRxOfflastValid[i]),
|
|
.TXN_RX_DONE_LEN(wChnlRxDoneLen[(`SIG_RXDONELEN_W*i) +: `SIG_RXDONELEN_W]),
|
|
.TXN_RX_DONE_ACK(wChnlRxDoneReady[i]),
|
|
|
|
.TXN_TX_ACK(wChnlTxLenReady[i]), // ACK'd on length read
|
|
.TXN_TX_LEN(wChnlTxReqLen[(`SIG_TXRLEN_W*i) +: `SIG_TXRLEN_W]),
|
|
.TXN_TX_OFF_LAST(wChnlTxOfflast[(`SIG_OFFLAST_W*i) +: `SIG_OFFLAST_W]),
|
|
.TXN_TX_DONE_LEN(wChnlTxDoneLen[(`SIG_TXDONELEN_W*i) +:`SIG_TXDONELEN_W]),
|
|
.TXN_TX_DONE_ACK(wChnlTxDoneReady[i]),
|
|
|
|
.RX_REQ(wTxEngRdReq[i]),
|
|
.RX_REQ_ACK(wTxEngRdAck[i]),
|
|
.RX_REQ_TAG(wTxEngRdSgChnl[(2*i) +:2]),// TODO: `SIG_INTERNALTAG_W
|
|
.RX_REQ_ADDR(wTxEngRdAddr[(`SIG_ADDR_W*i) +:`SIG_ADDR_W]),
|
|
.RX_REQ_LEN(wTxEngRdLen[(`SIG_LEN_W*i) +:`SIG_LEN_W]),
|
|
|
|
.TX_REQ(wTxEngWrReq[i]),
|
|
.TX_REQ_ACK(wTxEngWrAck[i]),
|
|
.TX_ADDR(wTxEngWrAddr[(`SIG_ADDR_W*i) +: `SIG_ADDR_W]),
|
|
.TX_LEN(wTxEngWrLen[(`SIG_LEN_W*i) +: `SIG_LEN_W]),
|
|
.TX_DATA(wTxEngWrData[(C_PCI_DATA_WIDTH*i) +:C_PCI_DATA_WIDTH]),
|
|
.TX_DATA_REN(wTxEngWrDataRen[i]),
|
|
.TX_SENT(wTxEngWrSent[i]),
|
|
|
|
.MAIN_DATA_EN(wRxEngMainDataEn[(C_PCI_DATA_WORD_WIDTH*i) +:C_PCI_DATA_WORD_WIDTH]),
|
|
.MAIN_DONE(wRxEngMainDone[i]),
|
|
.MAIN_ERR(wRxEngMainErr[i]),
|
|
|
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.SG_RX_DATA_EN(wRxEngSgRxDataEn[(C_PCI_DATA_WORD_WIDTH*i) +:C_PCI_DATA_WORD_WIDTH]),
|
|
.SG_RX_DONE(wRxEngSgRxDone[i]),
|
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.SG_RX_ERR(wRxEngSgRxErr[i]),
|
|
|
|
.SG_TX_DATA_EN(wRxEngSgTxDataEn[(C_PCI_DATA_WORD_WIDTH*i) +:C_PCI_DATA_WORD_WIDTH]),
|
|
.SG_TX_DONE(wRxEngSgTxDone[i]),
|
|
.SG_TX_ERR(wRxEngSgTxErr[i]),
|
|
|
|
.CHNL_RX_CLK(CHNL_RX_CLK[i]),
|
|
.CHNL_RX(CHNL_RX[i]),
|
|
.CHNL_RX_ACK(CHNL_RX_ACK[i]),
|
|
.CHNL_RX_LAST(CHNL_RX_LAST[i]),
|
|
.CHNL_RX_LEN(CHNL_RX_LEN[(32*i) +:32]),
|
|
.CHNL_RX_OFF(CHNL_RX_OFF[(31*i) +:31]),
|
|
.CHNL_RX_DATA(CHNL_RX_DATA[(C_PCI_DATA_WIDTH*i) +:C_PCI_DATA_WIDTH]),
|
|
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID[i]),
|
|
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN[i]),
|
|
|
|
.CHNL_TX_CLK(CHNL_TX_CLK[i]),
|
|
.CHNL_TX(CHNL_TX[i]),
|
|
.CHNL_TX_ACK(CHNL_TX_ACK[i]),
|
|
.CHNL_TX_LAST(CHNL_TX_LAST[i]),
|
|
.CHNL_TX_LEN(CHNL_TX_LEN[(32*i) +:32]),
|
|
.CHNL_TX_OFF(CHNL_TX_OFF[(31*i) +:31]),
|
|
.CHNL_TX_DATA(CHNL_TX_DATA[(C_PCI_DATA_WIDTH*i) +:C_PCI_DATA_WIDTH]),
|
|
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID[i]),
|
|
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN[i])
|
|
);
|
|
|
|
end
|
|
endgenerate
|
|
endmodule
|
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// Local Variables:
|
|
// verilog-library-directories:("." "registers/" "import")
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// End:
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|