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103 lines
4.7 KiB
Verilog
103 lines
4.7 KiB
Verilog
// ----------------------------------------------------------------------
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// Copyright (c) 2016, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Filename: one_hot_mux.v
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// Version: 1.00.a
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// Verilog Standard: Verilog-2001
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// Description: A mux module, where the output select is a one-hot bus
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// Author: Dustin Richmond
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//-----------------------------------------------------------------------------
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`timescale 1ns/1ns
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`include "functions.vh"
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module one_hot_mux
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#(parameter C_DATA_WIDTH = 1,
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parameter C_SELECT_WIDTH = 2,
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parameter C_AGGREGATE_WIDTH = C_SELECT_WIDTH*C_DATA_WIDTH
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)
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(
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input [C_SELECT_WIDTH-1:0] ONE_HOT_SELECT,
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input [C_AGGREGATE_WIDTH-1:0] ONE_HOT_INPUTS,
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output [C_DATA_WIDTH-1:0] ONE_HOT_OUTPUT);
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genvar i;
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wire [C_DATA_WIDTH-1:0] wOneHotInputs[(1<<C_SELECT_WIDTH):1];
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reg [C_DATA_WIDTH-1:0] _rOneHotOutput;
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assign ONE_HOT_OUTPUT = _rOneHotOutput;
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generate
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for( i = 0 ; i < C_SELECT_WIDTH; i = i + 1 ) begin : gen_input_array
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assign wOneHotInputs[(1<<i)] = ONE_HOT_INPUTS[C_DATA_WIDTH*i +: C_DATA_WIDTH];
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end
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if(C_SELECT_WIDTH == 1) begin
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always @(*) begin
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_rOneHotOutput = wOneHotInputs[1];
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end
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end else if(C_SELECT_WIDTH == 2) begin
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always @(*) begin
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case(ONE_HOT_SELECT)
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2'b01: _rOneHotOutput = wOneHotInputs[1];
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2'b10: _rOneHotOutput = wOneHotInputs[2];
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default:_rOneHotOutput = wOneHotInputs[1];
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endcase // case (ONE_HOT_SELECT)
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end
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end else if( C_SELECT_WIDTH == 4) begin
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always @(*) begin
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case(ONE_HOT_SELECT)
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4'b0001: _rOneHotOutput = wOneHotInputs[1];
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4'b0010: _rOneHotOutput = wOneHotInputs[2];
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4'b0100: _rOneHotOutput = wOneHotInputs[4];
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4'b1000: _rOneHotOutput = wOneHotInputs[8];
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default:_rOneHotOutput = wOneHotInputs[1];
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endcase // case (ONE_HOT_SELECT)
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end
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end else if( C_SELECT_WIDTH == 8) begin
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always @(*) begin
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case(ONE_HOT_SELECT)
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8'b00000001: _rOneHotOutput = wOneHotInputs[1];
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8'b00000010: _rOneHotOutput = wOneHotInputs[2];
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8'b00000100: _rOneHotOutput = wOneHotInputs[4];
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8'b00001000: _rOneHotOutput = wOneHotInputs[8];
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8'b00010000: _rOneHotOutput = wOneHotInputs[16];
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8'b00100000: _rOneHotOutput = wOneHotInputs[32];
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8'b01000000: _rOneHotOutput = wOneHotInputs[64];
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8'b10000000: _rOneHotOutput = wOneHotInputs[128];
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default:_rOneHotOutput = wOneHotInputs[1];
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endcase // case (ONE_HOT_SELECT)
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end
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end
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endgenerate
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endmodule
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