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89 lines
3.4 KiB
Systemverilog
89 lines
3.4 KiB
Systemverilog
// ----------------------------------------------------------------------
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// Copyright (c) 2016, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Filename: trellis.vh
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// Version: 1.0
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// Verilog Standard: Verilog-2001
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// Description: The trellis.vh file is a header file with many interface
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// width definitions for the Trellis stack
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// Author: Dustin Richmond (@darichmond)
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//-----------------------------------------------------------------------------
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`ifndef __TRELLIS_VH
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`define __TRELLIS_VH 1
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`include "widths.vh"
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`include "types.vh"
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`include "functions.vh"
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// PCIe Signals
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`define SIG_BARDECODE_W `BARDECODE_W
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`define SIG_OFFSET_W `OFFSET_W
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`define SIG_TC_W `TC_W
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`define SIG_ATTR_W `ATTR_W
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`define SIG_LEN_W `LEN_W
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`define SIG_TD_W `TD_W
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`define SIG_TYPE_W `EXT_TYPE_W
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`define SIG_FMT_W `FMT_W
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`define SIG_FBE_W `FBE_W
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`define SIG_LBE_W `LBE_W
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`define SIG_TAG_W `TAG_W
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`define SIG_REQID_W `REQID_W
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`define SIG_ADDR_W `ADDR_W
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`define SIG_BYTECNT_W `BYTECNT_W
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`define SIG_STAT_W `STAT_W
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`define SIG_CPLID_W `CPLID_W
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`define SIG_LOWADDR_W `LOWADDR_W
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`define SIG_CFGREG_W `PCIE_CONFIGURATION_REGISTER_WIDTH
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`define SIG_BUSID_W `PCIE_BUS_ID_WIDTH
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`define SIG_DEVID_W `PCIE_DEVICE_ID_WIDTH // Device ID Width
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`define SIG_FNID_W `PCIE_FUNCTION_ID_WIDTH // Function Number
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`define SIG_LINKWIDTH_W `LINKWIDTH_W
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`define SIG_LINKRATE_W `LINKRATE_W
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`define SIG_MAXREAD_W `MAXREAD_W
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`define SIG_MAXPAYLOAD_W `MAXPAYLOAD_W
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`define SIG_FC_CPLD_W 12
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`define SIG_FC_CPLH_W 8
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// The maximum number of alignment blanks that can be inserted in a packet is 7
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`define SIG_NONPAY_W 4
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`define SIG_PACKETLEN_W (clog2s(4096/4) + `SIG_NONPAY_W + 1)
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`define SIG_ALIGN_W 3
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`define SIG_HDRLEN_W 3
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`define SIG_MAXHDR_W 128
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`endif
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