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d5f3ba7309
The C_VALUE parameter sets the reset value of each bit in the shift register. All bits will get the same value, individual setting of reset values is not implemented.
81 lines
2.9 KiB
Verilog
81 lines
2.9 KiB
Verilog
// ----------------------------------------------------------------------
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// Copyright (c) 2015, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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/*
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Filename: scsdp.v
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Version: 1.0
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Verilog Standard: Verilog-2001
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Description: A simple, single clock, simple dual port (SCSDP) ram
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Notes: Any modifications to this file should meet the conditions set
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forth in the "Trellis Style Guide"
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Author: Dustin Richmond (@darichmond)
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Co-Authors:
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*/
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`timescale 1ns/1ns
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`include "functions.vh"
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module scsdpram
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#(
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parameter C_WIDTH = 32,
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parameter C_DEPTH = 1024
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)
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(
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input CLK,
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input RD1_EN,
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input [clog2s(C_DEPTH)-1:0] RD1_ADDR,
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output [C_WIDTH-1:0] RD1_DATA,
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input WR1_EN,
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input [clog2s(C_DEPTH)-1:0] WR1_ADDR,
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input [C_WIDTH-1:0] WR1_DATA
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);
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reg [C_WIDTH-1:0] rMemory [C_DEPTH-1:0];
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reg [C_WIDTH-1:0] rDataOut;
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assign RD1_DATA = rDataOut;
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always @(posedge CLK) begin
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if (WR1_EN) begin
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rMemory[WR1_ADDR] <= #1 WR1_DATA;
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end
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if(RD1_EN) begin
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rDataOut <= #1 rMemory[RD1_ADDR];
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end
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end
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endmodule
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