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110 lines
3.7 KiB
Verilog
110 lines
3.7 KiB
Verilog
// ----------------------------------------------------------------------
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// Copyright (c) 2015, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Filename: tx_port_buffer_32.v
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// Version: 1.00.a
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// Verilog Standard: Verilog-2001
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// Description: Wraps a FIFO for saving channel data and provides a
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// registered read output. Data is available 3 cycles after RD_EN is asserted
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// (not 1, like a traditional FIFO).
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// Author: Matt Jacobsen
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// History: @mattj: Version 2.0
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//-----------------------------------------------------------------------------
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`timescale 1ns/1ns
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module tx_port_buffer_32 #(
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parameter C_FIFO_DATA_WIDTH = 9'd32,
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parameter C_FIFO_DEPTH = 512,
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// Local parameters
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parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1)
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)
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(
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input RST,
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input CLK,
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input [C_FIFO_DATA_WIDTH-1:0] WR_DATA, // Input data
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input WR_EN, // Input data write enable
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output [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT, // Input data FIFO is full
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output [C_FIFO_DATA_WIDTH-1:0] RD_DATA, // Output data
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input RD_EN // Output data read enable
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);
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`include "functions.vh"
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reg rFifoRdEn=0, _rFifoRdEn=0;
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reg [C_FIFO_DATA_WIDTH-1:0] rFifoData={C_FIFO_DATA_WIDTH{1'd0}}, _rFifoData={C_FIFO_DATA_WIDTH{1'd0}};
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wire [C_FIFO_DATA_WIDTH-1:0] wFifoData;
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assign RD_DATA = rFifoData;
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// Buffer the input signals that come from outside the tx_port.
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always @ (posedge CLK) begin
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rFifoRdEn <= #1 (RST ? 1'd0 : _rFifoRdEn);
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end
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always @ (*) begin
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_rFifoRdEn = RD_EN;
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end
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// FIFO for storing data from the channel.
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(* RAM_STYLE="BLOCK" *)
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sync_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) fifo (
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.CLK(CLK),
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.RST(RST),
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.WR_EN(WR_EN),
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.WR_DATA(WR_DATA),
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.FULL(),
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.COUNT(WR_COUNT),
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.RD_EN(rFifoRdEn),
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.RD_DATA(wFifoData),
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.EMPTY()
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);
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// Buffer data from the FIFO.
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always @ (posedge CLK) begin
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rFifoData <= #1 _rFifoData;
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end
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always @ (*) begin
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_rFifoData = wFifoData;
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end
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endmodule
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