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dc93333b9c
The error occured when calculating the actual header fifo depth, C_ACTUAL_FIFO_DEPTH. This was initially clog2(C_FIFO_DEPTH), but should have been 1<<clog2(C_FIFO_DEPTH).
226 lines
11 KiB
Verilog
226 lines
11 KiB
Verilog
// ----------------------------------------------------------------------
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// Copyright (c) 2015, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Filename: tx_engine.v
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// Version: 1.0
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// Verilog Standard: Verilog-2001
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// Description: The tx_engine module takes a formatted header, number of alignment
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// blanks and a payloa and concatenates all three (in that order) to form a
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// packet. These packets must meet max-request, max-payload, and payload
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// termination requirements (see Read Completion Boundary). The tx_engine does
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// not check these requirements during operation, but may do so during simulation.
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// This Engine is capable of operating at "line rate".
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// Author: Dustin Richmond (@darichmond)
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//-----------------------------------------------------------------------------
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`timescale 1ns/1ns
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`include "trellis.vh" // Defines the user-facing signal widths.
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module tx_engine
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#(parameter C_DATA_WIDTH = 128,
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parameter C_DEPTH_PACKETS = 10,
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parameter C_PIPELINE_INPUT = 1,
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parameter C_PIPELINE_OUTPUT = 0,
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parameter C_FORMATTER_DELAY = 1,
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parameter C_MAX_HDR_WIDTH = 128,
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parameter C_MAX_PAYLOAD_DWORDS = 64,
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parameter C_VENDOR = "ALTERA"
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)
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(
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// Interface: Clocks
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input CLK,
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// Interface: Reset
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input RST_IN,
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// Interface: TX HDR
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input TX_HDR_VALID,
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input [C_MAX_HDR_WIDTH-1:0] TX_HDR,
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input [`SIG_LEN_W-1:0] TX_HDR_PAYLOAD_LEN,
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input [`SIG_NONPAY_W-1:0] TX_HDR_NONPAY_LEN,
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input [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,
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input TX_HDR_NOPAYLOAD,
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output TX_HDR_READY,
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// Interface: TX_DATA
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input TX_DATA_VALID,
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input [C_DATA_WIDTH-1:0] TX_DATA,
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input TX_DATA_START_FLAG,
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input [clog2s(C_DATA_WIDTH/32)-1:0] TX_DATA_START_OFFSET,
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input TX_DATA_END_FLAG,
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input [clog2s(C_DATA_WIDTH/32)-1:0] TX_DATA_END_OFFSET,
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output TX_DATA_READY,
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// Interface: TX_PKT
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input TX_PKT_READY,
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output [C_DATA_WIDTH-1:0] TX_PKT,
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output TX_PKT_START_FLAG,
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output [clog2s(C_DATA_WIDTH/32)-1:0] TX_PKT_START_OFFSET,
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output TX_PKT_END_FLAG,
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output [clog2s(C_DATA_WIDTH/32)-1:0] TX_PKT_END_OFFSET,
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output TX_PKT_VALID
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);
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localparam C_PIPELINE_HDR_FIFO_INPUT = C_PIPELINE_INPUT;
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localparam C_PIPELINE_HDR_FIFO_OUTPUT = C_PIPELINE_OUTPUT;
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localparam C_PIPELINE_HDR_INPUT = C_PIPELINE_INPUT;
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localparam C_ACTUAL_HDR_FIFO_DEPTH = (1<<clog2s(C_DEPTH_PACKETS));
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localparam C_USE_COMPUTE_REG = 1;
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localparam C_USE_READY_REG = 1;
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localparam C_USE_FWFT_HDR_FIFO = 1;
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localparam C_DATA_FIFO_DEPTH = C_ACTUAL_HDR_FIFO_DEPTH + C_FORMATTER_DELAY +
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C_PIPELINE_HDR_FIFO_INPUT + C_PIPELINE_HDR_FIFO_OUTPUT + C_USE_FWFT_HDR_FIFO + // Header Fifo
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C_PIPELINE_HDR_INPUT + C_USE_COMPUTE_REG + C_USE_READY_REG + C_PIPELINE_OUTPUT + 1; // Aligner TODO: Why +1. Is it 64-bit specific?
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wire wTxHdrReady;
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wire wTxHdrValid;
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wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
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wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
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wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
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wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
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wire wTxHdrNoPayload;
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wire wTxDataReady;
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wire [C_DATA_WIDTH-1:0] wTxData;
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wire [clog2s(C_DATA_WIDTH/32)-1:0] wTxDataEndOffset;
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wire wTxDataStartFlag;
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wire wTxDataPacketValid;
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wire [(C_DATA_WIDTH/32)-1:0] wTxDataEndFlags;
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wire [(C_DATA_WIDTH/32)-1:0] wTxDataWordValid;
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wire [(C_DATA_WIDTH/32)-1:0] wTxDataWordReady;
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tx_data_pipeline
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#(.C_DEPTH_PACKETS (C_DATA_FIFO_DEPTH),
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/*AUTOINSTPARAM*/
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// Parameters
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.C_DATA_WIDTH (C_DATA_WIDTH),
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.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
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.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
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.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS),
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.C_VENDOR (C_VENDOR))
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tx_data_pipeline_inst
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(// Outputs
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.RD_TX_DATA (wTxData[C_DATA_WIDTH-1:0]),
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.RD_TX_DATA_WORD_VALID (wTxDataWordValid[(C_DATA_WIDTH/32)-1:0]),
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.RD_TX_DATA_START_FLAG (wTxDataStartFlag),
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.RD_TX_DATA_END_FLAGS (wTxDataEndFlags[(C_DATA_WIDTH/32)-1:0]),
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.RD_TX_DATA_PACKET_VALID (wTxDataPacketValid),
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.WR_TX_DATA_READY (TX_DATA_READY),
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// Inputs
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.RD_TX_DATA_WORD_READY (wTxDataWordReady[(C_DATA_WIDTH/32)-1:0]),
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.WR_TX_DATA (TX_DATA),
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.WR_TX_DATA_VALID (TX_DATA_VALID),
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.WR_TX_DATA_START_FLAG (TX_DATA_START_FLAG),
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.WR_TX_DATA_START_OFFSET (TX_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
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.WR_TX_DATA_END_FLAG (TX_DATA_END_FLAG),
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.WR_TX_DATA_END_OFFSET (TX_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN));
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// TX Header Fifo
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tx_hdr_fifo
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#(.C_PIPELINE_OUTPUT (C_PIPELINE_HDR_FIFO_OUTPUT),
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.C_PIPELINE_INPUT (C_PIPELINE_HDR_FIFO_INPUT),
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/*AUTOINSTPARAM*/
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// Parameters
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.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
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.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
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.C_VENDOR (C_VENDOR))
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txhf_inst
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(// Outputs
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.WR_TX_HDR_READY (TX_HDR_READY),
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.RD_TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
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.RD_TX_HDR_VALID (wTxHdrValid),
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.RD_TX_HDR_NOPAYLOAD (wTxHdrNoPayload),
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.RD_TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
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.RD_TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
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.RD_TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
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// Inputs
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.WR_TX_HDR (TX_HDR[C_MAX_HDR_WIDTH-1:0]),
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.WR_TX_HDR_VALID (TX_HDR_VALID),
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.WR_TX_HDR_NOPAYLOAD (TX_HDR_NOPAYLOAD),
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.WR_TX_HDR_PAYLOAD_LEN (TX_HDR_PAYLOAD_LEN[`SIG_LEN_W-1:0]),
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.WR_TX_HDR_NONPAY_LEN (TX_HDR_NONPAY_LEN[`SIG_NONPAY_W-1:0]),
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.WR_TX_HDR_PACKET_LEN (TX_HDR_PACKET_LEN[`SIG_PACKETLEN_W-1:0]),
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.RD_TX_HDR_READY (wTxHdrReady),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN));
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// TX Header Fifo
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tx_alignment_pipeline
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#(// Parameters
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.C_PIPELINE_OUTPUT (1),
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.C_PIPELINE_DATA_INPUT (1),
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.C_PIPELINE_HDR_INPUT (C_PIPELINE_HDR_INPUT),
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.C_DATA_WIDTH (C_DATA_WIDTH),
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// Parameters
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/*AUTOINSTPARAM*/
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// Parameters
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.C_USE_COMPUTE_REG (C_USE_COMPUTE_REG),
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.C_USE_READY_REG (C_USE_READY_REG),
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.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
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.C_VENDOR (C_VENDOR))
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tx_alignment_inst
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(// Outputs
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.TX_DATA_WORD_READY (wTxDataWordReady[(C_DATA_WIDTH/32)-1:0]),
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.TX_HDR_READY (wTxHdrReady),
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// Inputs
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.TX_DATA_START_FLAG (wTxDataStartFlag),
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.TX_DATA_END_FLAGS (wTxDataEndFlags),
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.TX_DATA_WORD_VALID (wTxDataWordValid[(C_DATA_WIDTH/32)-1:0]),
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.TX_DATA_PACKET_VALID (wTxDataPacketValid),
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.TX_DATA (wTxData[C_DATA_WIDTH-1:0]),
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.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
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.TX_HDR_VALID (wTxHdrValid),
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.TX_HDR_NOPAYLOAD (wTxHdrNoPayload),
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.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
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.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
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.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
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/*AUTOINST*/
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// Outputs
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.TX_PKT (TX_PKT[C_DATA_WIDTH-1:0]),
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.TX_PKT_START_FLAG (TX_PKT_START_FLAG),
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.TX_PKT_START_OFFSET (TX_PKT_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
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.TX_PKT_END_FLAG (TX_PKT_END_FLAG),
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.TX_PKT_END_OFFSET (TX_PKT_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
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.TX_PKT_VALID (TX_PKT_VALID),
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN),
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.TX_PKT_READY (TX_PKT_READY));
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endmodule
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