mirror of
https://github.com/KastnerRG/riffa.git
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256 lines
9.6 KiB
Verilog
256 lines
9.6 KiB
Verilog
// ----------------------------------------------------------------------
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// Copyright (c) 2015, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Filename: channel_32.v
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// Version: 1.00.a
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// Verilog Standard: Verilog-2001
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// Description: Represents a RIFFA channel. Contains a RX port and a
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// TX port.
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// Author: Matt Jacobsen
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// History: @mattj: Version 2.0
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//-----------------------------------------------------------------------------
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`timescale 1ns/1ns
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module channel_32 #(
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parameter C_DATA_WIDTH = 9'd32,
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parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
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// Local parameters
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parameter C_RX_FIFO_DEPTH = 1024,
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parameter C_TX_FIFO_DEPTH = 512,
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parameter C_SG_FIFO_DEPTH = 1024,
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parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1)
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)
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(
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input CLK,
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input RST,
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input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
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input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
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input [31:0] PIO_DATA, // Single word programmed I/O data
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input [C_DATA_WIDTH-1:0] ENG_DATA, // Main incoming data
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output SG_RX_BUF_RECVD, // Scatter gather RX buffer completely read (ready for next if applicable)
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input SG_RX_BUF_LEN_VALID, // Scatter gather RX buffer length valid
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input SG_RX_BUF_ADDR_HI_VALID, // Scatter gather RX buffer high address valid
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input SG_RX_BUF_ADDR_LO_VALID, // Scatter gather RX buffer low address valid
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output SG_TX_BUF_RECVD, // Scatter gather TX buffer completely read (ready for next if applicable)
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input SG_TX_BUF_LEN_VALID, // Scatter gather TX buffer length valid
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input SG_TX_BUF_ADDR_HI_VALID, // Scatter gather TX buffer high address valid
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input SG_TX_BUF_ADDR_LO_VALID, // Scatter gather TX buffer low address valid
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input TXN_RX_LEN_VALID, // Read transaction length valid
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input TXN_RX_OFF_LAST_VALID, // Read transaction offset/last valid
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output [31:0] TXN_RX_DONE_LEN, // Read transaction actual transfer length
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output TXN_RX_DONE, // Read transaction done
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input TXN_RX_DONE_ACK, // Read transaction actual transfer length read
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output TXN_TX, // Write transaction notification
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input TXN_TX_ACK, // Write transaction acknowledged
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output [31:0] TXN_TX_LEN, // Write transaction length
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output [31:0] TXN_TX_OFF_LAST, // Write transaction offset/last
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output [31:0] TXN_TX_DONE_LEN, // Write transaction actual transfer length
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output TXN_TX_DONE, // Write transaction done
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input TXN_TX_DONE_ACK, // Write transaction actual transfer length read
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output RX_REQ, // Read request
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input RX_REQ_ACK, // Read request accepted
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output [1:0] RX_REQ_TAG, // Read request data tag
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output [63:0] RX_REQ_ADDR, // Read request address
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output [9:0] RX_REQ_LEN, // Read request length
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output TX_REQ, // Outgoing write request
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input TX_REQ_ACK, // Outgoing write request acknowledged
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output [63:0] TX_ADDR, // Outgoing write high address
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output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
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output [C_DATA_WIDTH-1:0] TX_DATA, // Outgoing write data
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input TX_DATA_REN, // Outgoing write data read enable
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input TX_SENT, // Outgoing write complete
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input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN, // Main incoming data enable
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input MAIN_DONE, // Main incoming data complete
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input MAIN_ERR, // Main incoming data completed with error
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input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN, // Scatter gather for RX incoming data enable
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input SG_RX_DONE, // Scatter gather for RX incoming data complete
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input SG_RX_ERR, // Scatter gather for RX incoming data completed with error
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input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN, // Scatter gather for TX incoming data enable
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input SG_TX_DONE, // Scatter gather for TX incoming data complete
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input SG_TX_ERR, // Scatter gather for TX incoming data completed with error
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input CHNL_RX_CLK, // Channel read clock
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output CHNL_RX, // Channel read receive signal
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input CHNL_RX_ACK, // Channle read received signal
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output CHNL_RX_LAST, // Channel last read
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output [31:0] CHNL_RX_LEN, // Channel read length
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output [30:0] CHNL_RX_OFF, // Channel read offset
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output [C_DATA_WIDTH-1:0] CHNL_RX_DATA, // Channel read data
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output CHNL_RX_DATA_VALID, // Channel read data valid
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input CHNL_RX_DATA_REN, // Channel read data has been recieved
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input CHNL_TX_CLK, // Channel write clock
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input CHNL_TX, // Channel write receive signal
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output CHNL_TX_ACK, // Channel write acknowledgement signal
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input CHNL_TX_LAST, // Channel last write
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input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
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input [30:0] CHNL_TX_OFF, // Channel write offset
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input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
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input CHNL_TX_DATA_VALID, // Channel write data valid
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output CHNL_TX_DATA_REN // Channel write data has been recieved
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);
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`include "functions.vh"
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wire [C_DATA_WIDTH-1:0] wTxSgData;
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wire wTxSgDataEmpty;
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wire wTxSgDataRen;
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wire wTxSgDataErr;
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wire wTxSgDataRst;
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// Receiving port (data to the channel)
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rx_port_32 #(
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.C_DATA_WIDTH(C_DATA_WIDTH),
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.C_MAIN_FIFO_DEPTH(C_RX_FIFO_DEPTH),
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.C_SG_FIFO_DEPTH(C_SG_FIFO_DEPTH),
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.C_MAX_READ_REQ(C_MAX_READ_REQ)
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) rxPort (
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.RST(RST),
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.CLK(CLK),
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.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
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.SG_RX_BUF_RECVD(SG_RX_BUF_RECVD),
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.SG_RX_BUF_DATA(PIO_DATA),
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.SG_RX_BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
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.SG_RX_BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
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.SG_RX_BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
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.SG_TX_BUF_RECVD(SG_TX_BUF_RECVD),
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.SG_TX_BUF_DATA(PIO_DATA),
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.SG_TX_BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
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.SG_TX_BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
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.SG_TX_BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
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.SG_DATA(wTxSgData),
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.SG_DATA_EMPTY(wTxSgDataEmpty),
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.SG_DATA_REN(wTxSgDataRen),
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.SG_RST(wTxSgDataRst),
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.SG_ERR(wTxSgDataErr),
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.TXN_DATA(PIO_DATA),
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.TXN_LEN_VALID(TXN_RX_LEN_VALID),
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.TXN_OFF_LAST_VALID(TXN_RX_OFF_LAST_VALID),
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.TXN_DONE_LEN(TXN_RX_DONE_LEN),
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.TXN_DONE(TXN_RX_DONE),
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.TXN_DONE_ACK(TXN_RX_DONE_ACK),
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.RX_REQ(RX_REQ),
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.RX_REQ_ACK(RX_REQ_ACK),
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.RX_REQ_TAG(RX_REQ_TAG),
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.RX_REQ_ADDR(RX_REQ_ADDR),
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.RX_REQ_LEN(RX_REQ_LEN),
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.MAIN_DATA(ENG_DATA),
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.MAIN_DATA_EN(MAIN_DATA_EN),
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.MAIN_DONE(MAIN_DONE),
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.MAIN_ERR(MAIN_ERR),
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.SG_RX_DATA(ENG_DATA),
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.SG_RX_DATA_EN(SG_RX_DATA_EN),
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.SG_RX_DONE(SG_RX_DONE),
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.SG_RX_ERR(SG_RX_ERR),
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.SG_TX_DATA(ENG_DATA),
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.SG_TX_DATA_EN(SG_TX_DATA_EN),
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.SG_TX_DONE(SG_TX_DONE),
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.SG_TX_ERR(SG_TX_ERR),
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.CHNL_CLK(CHNL_RX_CLK),
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.CHNL_RX(CHNL_RX),
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.CHNL_RX_ACK(CHNL_RX_ACK),
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.CHNL_RX_LAST(CHNL_RX_LAST),
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.CHNL_RX_LEN(CHNL_RX_LEN),
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.CHNL_RX_OFF(CHNL_RX_OFF),
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.CHNL_RX_DATA(CHNL_RX_DATA),
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.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID),
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.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
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);
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// Sending port (data from the channel)
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tx_port_32 #(
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.C_DATA_WIDTH(C_DATA_WIDTH),
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.C_FIFO_DEPTH(C_TX_FIFO_DEPTH)
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) txPort (
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.CLK(CLK),
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.RST(RST),
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.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
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.TXN(TXN_TX),
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.TXN_ACK(TXN_TX_ACK),
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.TXN_LEN(TXN_TX_LEN),
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.TXN_OFF_LAST(TXN_TX_OFF_LAST),
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.TXN_DONE_LEN(TXN_TX_DONE_LEN),
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.TXN_DONE(TXN_TX_DONE),
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.TXN_DONE_ACK(TXN_TX_DONE_ACK),
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.SG_DATA(wTxSgData),
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.SG_DATA_EMPTY(wTxSgDataEmpty),
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.SG_DATA_REN(wTxSgDataRen),
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.SG_RST(wTxSgDataRst),
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.SG_ERR(wTxSgDataErr),
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.TX_REQ(TX_REQ),
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.TX_REQ_ACK(TX_REQ_ACK),
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.TX_ADDR(TX_ADDR),
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.TX_LEN(TX_LEN),
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.TX_DATA(TX_DATA),
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.TX_DATA_REN(TX_DATA_REN),
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.TX_SENT(TX_SENT),
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.CHNL_CLK(CHNL_TX_CLK),
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.CHNL_TX(CHNL_TX),
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.CHNL_TX_ACK(CHNL_TX_ACK),
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.CHNL_TX_LAST(CHNL_TX_LAST),
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.CHNL_TX_LEN(CHNL_TX_LEN),
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.CHNL_TX_OFF(CHNL_TX_OFF),
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.CHNL_TX_DATA(CHNL_TX_DATA),
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.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
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.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
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);
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endmodule
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