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73 lines
3.2 KiB
Verilog
73 lines
3.2 KiB
Verilog
// ----------------------------------------------------------------------
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// Copyright (c) 2015, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Filename: counter.v
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// Version: 1.00.a
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// Verilog Standard: Verilog-2001
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// Description: A simple up-counter. The maximum value is the largest expected
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// value. The counter will not pass the SAT_VALUE. If the SAT_VALUE > MAX_VALUE,
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// the counter will roll over and never stop. On RST_IN, the counter
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// synchronously resets to the RST_VALUE
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// Author: Dustin Richmond (@darichmond)
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//-----------------------------------------------------------------------------
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`timescale 1ns/1ns
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`include "functions.vh"
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module counter
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#(parameter C_MAX_VALUE = 10,
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parameter C_SAT_VALUE = 10,
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parameter C_RST_VALUE = 0)
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(
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input CLK,
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input RST_IN,
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input ENABLE,
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output [clog2s(C_MAX_VALUE+1)-1:0] VALUE
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);
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wire wEnable;
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reg [clog2s(C_MAX_VALUE+1)-1:0] wCtrValue;
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reg [clog2s(C_MAX_VALUE+1)-1:0] rCtrValue;
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/* verilator lint_off WIDTH */
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assign wEnable = ENABLE & (C_SAT_VALUE > rCtrValue);
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/* verilator lint_on WIDTH */
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assign VALUE = rCtrValue;
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always @(posedge CLK) begin
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if(RST_IN) begin
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rCtrValue <= C_RST_VALUE[clog2s(C_MAX_VALUE+1)-1:0];
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end else if(wEnable) begin
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rCtrValue <= rCtrValue + 1;
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end
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end
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endmodule
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