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75 lines
3.2 KiB
Verilog
75 lines
3.2 KiB
Verilog
// ----------------------------------------------------------------------
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// Copyright (c) 2015, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Filename: ram_2clk_1w_1r.v
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// Version: 1.00.a
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// Verilog Standard: Verilog-2001
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// Description: An inferrable RAM module. Dual clocks, 1 write port, 1
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// read port. In Xilinx designs, specify RAM_STYLE="BLOCK"
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// to use BRAM memory or RAM_STYLE="DISTRIBUTED" to use
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// LUT memory.
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// Author: Matt Jacobsen
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// History: @mattj: Version 2.0
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//-----------------------------------------------------------------------------
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`timescale 1ns/1ns
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`include "functions.vh"
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module ram_2clk_1w_1r
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#(
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parameter C_RAM_WIDTH = 32,
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parameter C_RAM_DEPTH = 1024
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)
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(
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input CLKA,
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input CLKB,
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input WEA,
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input [clog2s(C_RAM_DEPTH)-1:0] ADDRA,
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input [clog2s(C_RAM_DEPTH)-1:0] ADDRB,
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input [C_RAM_WIDTH-1:0] DINA,
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output [C_RAM_WIDTH-1:0] DOUTB
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);
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//Local parameters
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localparam C_RAM_ADDR_BITS = clog2s(C_RAM_DEPTH);
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reg [C_RAM_WIDTH-1:0] rRAM [C_RAM_DEPTH-1:0];
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reg [C_RAM_WIDTH-1:0] rDout;
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assign DOUTB = rDout;
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always @(posedge CLKA) begin
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if (WEA)
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rRAM[ADDRA] <= #1 DINA;
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end
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always @(posedge CLKB) begin
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rDout <= #1 rRAM[ADDRB];
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end
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endmodule
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