mirror of
https://github.com/KastnerRG/riffa.git
synced 2024-12-24 22:58:54 +08:00
ad90d61584
Expanded DONE_RST into four signals, for each of the four engine interfaces. In the ultrascale engines, wired up all of the RST and DONE_RST signals. Quickly tested the logic in a power-on-reset like situation, no guarantees on graceful in-transmission resets. Classic engines will have to wait.
347 lines
17 KiB
Verilog
347 lines
17 KiB
Verilog
`include "trellis.vh"
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`include "tlp.vh"
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module rxc_engine_128
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#(parameter C_PCI_DATA_WIDTH = 128,
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parameter C_RX_PIPELINE_DEPTH=10)
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(// Interface: Clocks
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input CLK,
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// Interface: Resets
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input RST_BUS, // Replacement for generic RST_IN
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input RST_LOGIC, // Addition for RIFFA_RST
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output DONE_RXC_RST,
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// Interface: RX Classic
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input [C_PCI_DATA_WIDTH-1:0] RX_TLP,
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input RX_TLP_VALID,
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input RX_TLP_START_FLAG,
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input [`SIG_OFFSET_W-1:0] RX_TLP_START_OFFSET,
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input RX_TLP_END_FLAG,
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input [`SIG_OFFSET_W-1:0] RX_TLP_END_OFFSET,
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input [`SIG_BARDECODE_W-1:0] RX_TLP_BAR_DECODE,
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// Interface: RXC Engine
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output [C_PCI_DATA_WIDTH-1:0] RXC_DATA,
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output RXC_DATA_VALID,
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output [(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_WORD_ENABLE,
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output RXC_DATA_START_FLAG,
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output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_START_OFFSET,
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output RXC_DATA_END_FLAG,
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output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_END_OFFSET,
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output [`SIG_LBE_W-1:0] RXC_META_LDWBE,
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output [`SIG_FBE_W-1:0] RXC_META_FDWBE,
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output [`SIG_TAG_W-1:0] RXC_META_TAG,
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output [`SIG_LOWADDR_W-1:0] RXC_META_ADDR,
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output [`SIG_TYPE_W-1:0] RXC_META_TYPE,
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output [`SIG_LEN_W-1:0] RXC_META_LENGTH,
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output [`SIG_BYTECNT_W-1:0] RXC_META_BYTES_REMAINING,
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output [`SIG_CPLID_W-1:0] RXC_META_COMPLETER_ID,
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output RXC_META_EP,
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// Interface: RX Shift Register
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input [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] RX_SR_DATA,
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input [C_RX_PIPELINE_DEPTH:0] RX_SR_EOP,
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input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0] RX_SR_END_OFFSET,
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input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0] RX_SR_START_OFFSET,
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input [C_RX_PIPELINE_DEPTH:0] RX_SR_SOP,
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input [C_RX_PIPELINE_DEPTH:0] RX_SR_VALID
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);
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/*AUTOWIRE*/
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///*AUTOOUTPUT*/
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localparam C_RX_BE_W = (`SIG_FBE_W+`SIG_LBE_W);
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localparam C_RX_INPUT_STAGES = 1;
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localparam C_RX_OUTPUT_STAGES = 1;
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localparam C_RX_COMPUTATION_STAGES = 1;
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localparam C_RX_HDR_STAGES = 1; // Specific to the Xilinx 128-bit RXC Engine
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localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES + C_RX_HDR_STAGES;
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localparam C_OFFSET_WIDTH = clog2s(C_PCI_DATA_WIDTH/32);
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localparam C_STRADDLE_W = 64;
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localparam C_HDR_NOSTRADDLE_I = C_RX_INPUT_STAGES * C_PCI_DATA_WIDTH;
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localparam C_OUTPUT_STAGE_WIDTH = (C_PCI_DATA_WIDTH/32) + 2 + clog2s(C_PCI_DATA_WIDTH/32) + 1 + `SIG_TAG_W + `SIG_TYPE_W + `SIG_LOWADDR_W + `SIG_REQID_W + `SIG_LEN_W + `SIG_BYTECNT_W;
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// Header Reg Inputs
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wire [`SIG_OFFSET_W-1:0] __wRxcStartOffset;
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wire [`SIG_OFFSET_W-1:0] __wRxcStraddledStartOffset;
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wire [`TLP_MAXHDR_W-1:0] __wRxcHdr;
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wire [`TLP_MAXHDR_W-1:0] __wRxcHdrStraddled;
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wire [`TLP_MAXHDR_W-1:0] __wRxcHdrNotStraddled;
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wire __wRxcHdrStraddle;
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wire __wRxcHdrValid;
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wire __wRxcHdrSOP;
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wire __wRxcHdrSOPStraddle;
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// Header Reg Outputs
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wire _wRxcHdrValid;
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wire _wRxcHdrStraddle;
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wire _wRxcHdrSOPStraddle;
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wire _wRxcHdrSOP;
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wire [`TLP_MAXHDR_W-1:0] _wRxcHdr;
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wire _wRxcHdrSF;
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wire [2:0] _wRxcHdrDataSoff;
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wire _wRxcHdrEF;
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wire [1:0] _wRxcHdrDataEoff;
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wire _wRxcHdrSCP; // Single Cycle Packet
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wire _wRxcHdrMCP; // Multi Cycle Packet
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wire _wRxcHdrRegSF;
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wire _wRxcHdrRegValid;
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wire _wRxcHdrStartFlag;
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wire _wRxcHdr3DWHSF;
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wire [3:0] _wRxcHdrStartMask;
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wire [3:0] _wRxcHdrEndMask;
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// Header Reg Outputs
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wire [`TLP_MAXHDR_W-1:0] wRxcHdr;
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wire wRxcHdrSF;
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wire wRxcHdrEF;
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wire wRxcHdrValid;
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wire [63:0] wRxcMetadata;
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wire [`TLP_TYPE_W-1:0] wRxcType;
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wire [`TLP_LEN_W-1:0] wRxcLength;
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wire [2:0] wRxcHdrLength;// TODO:
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wire [`SIG_OFFSET_W-1:0] wRxcHdrStartOffset;// TODO:
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wire wRxcHdrSCP; // Single Cycle Packet
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wire wRxcHdrMCP; // Multi Cycle Packet
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wire [1:0] wRxcHdrDataSoff;
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wire [3:0] wRxcHdrStartMask;
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wire [3:0] wRxcHdrEndMask;
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// Output Register Inputs
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wire [C_PCI_DATA_WIDTH-1:0] wRxcData;
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wire wRxcDataValid;
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wire [(C_PCI_DATA_WIDTH/32)-1:0] wRxcDataWordEnable;
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wire wRxcDataStartFlag;
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wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wRxcDataStartOffset;
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wire wRxcDataEndFlag;
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wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wRxcDataEndOffset;
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wire [`SIG_TAG_W-1:0] wRxcMetaTag;
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wire [`SIG_TYPE_W-1:0] wRxcMetaType;
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wire [`SIG_LOWADDR_W-1:0] wRxcMetaAddr;
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wire [`SIG_REQID_W-1:0] wRxcMetaCompleterId;
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wire [`SIG_LEN_W-1:0] wRxcMetaLength;
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wire wRxcMetaEP;
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wire [`SIG_BYTECNT_W-1:0] wRxcMetaBytesRemaining;
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reg rStraddledSOP;
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reg rStraddledSOPSplit;
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// ----- Header Register -----
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assign __wRxcHdrSOP = RX_SR_SOP[C_RX_INPUT_STAGES] & ~__wRxcStartOffset[1];
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assign __wRxcHdrSOPStraddle = RX_SR_SOP[C_RX_INPUT_STAGES] & __wRxcStraddledStartOffset[1];
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assign __wRxcHdrNotStraddled = RX_SR_DATA[C_HDR_NOSTRADDLE_I +: C_PCI_DATA_WIDTH];
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assign __wRxcHdrStraddled = {RX_SR_DATA[C_RX_INPUT_STAGES*C_PCI_DATA_WIDTH +: C_STRADDLE_W],
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RX_SR_DATA[(C_RX_INPUT_STAGES+1)*C_PCI_DATA_WIDTH + C_STRADDLE_W +: C_STRADDLE_W ]};
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assign __wRxcStartOffset = RX_SR_START_OFFSET[`SIG_OFFSET_W*C_RX_INPUT_STAGES +: `SIG_OFFSET_W];
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assign __wRxcStraddledStartOffset = RX_SR_START_OFFSET[`SIG_OFFSET_W*(C_RX_INPUT_STAGES) +: `SIG_OFFSET_W];
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assign __wRxcHdrValid = __wRxcHdrSOP | ((rStraddledSOP | rStraddledSOPSplit) & RX_SR_VALID[C_RX_INPUT_STAGES]);
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assign _wRxcHdrRegSF = RX_SR_SOP[C_RX_INPUT_STAGES + C_RX_HDR_STAGES] & _wRxcHdrValid;
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assign _wRxcHdrDataSoff = {1'b0,_wRxcHdrSOPStraddle,1'b0} + 3'd3;
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assign _wRxcHdrRegValid = RX_SR_VALID[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
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assign _wRxcHdr3DWHSF = ~_wRxcHdr[`TLP_4DWHBIT_I] & _wRxcHdrSOP;
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assign _wRxcHdrSF = (_wRxcHdr3DWHSF | _wRxcHdrSOPStraddle);
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assign _wRxcHdrEF = RX_SR_EOP[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
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assign _wRxcHdrDataEoff = RX_SR_END_OFFSET[(C_RX_INPUT_STAGES+C_RX_HDR_STAGES)*`SIG_OFFSET_W +: C_OFFSET_WIDTH];
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assign _wRxcHdrSCP = _wRxcHdrSF & _wRxcHdrEF & (_wRxcHdr[`TLP_TYPE_R] == `TLP_TYPE_CPL);
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assign _wRxcHdrMCP = (_wRxcHdrSF & ~_wRxcHdrEF & (_wRxcHdr[`TLP_TYPE_R] == `TLP_TYPE_CPL)) |
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(wRxcHdrMCP & ~wRxcHdrEF);
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assign _wRxcHdrStartMask = 4'hf << (_wRxcHdrSF ? _wRxcHdrDataSoff[1:0] : 0);
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assign wRxcDataWordEnable = wRxcHdrEndMask & wRxcHdrStartMask & {4{wRxcDataValid}};
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assign wRxcDataValid = wRxcHdrSCP | wRxcHdrMCP;
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assign wRxcDataStartFlag = wRxcHdrSF;
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assign wRxcDataEndFlag = wRxcHdrEF;
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assign wRxcDataStartOffset = wRxcHdrDataSoff;
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assign wRxcMetaBytesRemaining = wRxcHdr[`TLP_CPLBYTECNT_R];
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assign wRxcMetaTag = wRxcHdr[`TLP_CPLTAG_R];
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assign wRxcMetaAddr = wRxcHdr[`TLP_CPLADDR_R];
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assign wRxcMetaCompleterId = wRxcHdr[`TLP_REQREQID_R];
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assign wRxcMetaLength = wRxcHdr[`TLP_LEN_R];
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assign wRxcMetaEP = wRxcHdr[`TLP_EP_R];
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assign wRxcMetaType = tlp_to_trellis_type({wRxcHdr[`TLP_FMT_R],wRxcHdr[`TLP_TYPE_R]});
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assign RXC_DATA = RX_SR_DATA[C_PCI_DATA_WIDTH*C_TOTAL_STAGES +: C_PCI_DATA_WIDTH];
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assign RXC_DATA_END_OFFSET = RX_SR_END_OFFSET[`SIG_OFFSET_W*(C_TOTAL_STAGES) +: C_OFFSET_WIDTH];
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always @(posedge CLK) begin
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rStraddledSOP <= RX_SR_SOP[C_RX_INPUT_STAGES] & __wRxcStraddledStartOffset[1];
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// Set Straddled SOP Split when there is a straddled packet where the
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// header is not contiguous. (Not sure if this is ever possible, but
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// better safe than sorry assert Straddled SOP Split. See Virtex 6 PCIe
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// errata.)
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if(__wRxcHdrSOP | RST_IN) begin
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rStraddledSOPSplit <=0;
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end else begin
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rStraddledSOPSplit <= (rStraddledSOP | rStraddledSOPSplit) & ~RX_SR_VALID[C_RX_INPUT_STAGES];
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end
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end
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mux
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#(
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// Parameters
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.C_NUM_INPUTS (2),
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.C_CLOG_NUM_INPUTS (1),
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.C_WIDTH (`TLP_MAXHDR_W),
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.C_MUX_TYPE ("SELECT")
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/*AUTOINSTPARAM*/)
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hdr_mux
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(
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// Outputs
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.MUX_OUTPUT (__wRxcHdr[`TLP_MAXHDR_W-1:0]),
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// Inputs
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.MUX_INPUTS ({__wRxcHdrStraddled[`TLP_MAXHDR_W-1:0],
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__wRxcHdrNotStraddled[`TLP_MAXHDR_W-1:0]}),
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.MUX_SELECT (rStraddledSOP | rStraddledSOPSplit)
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/*AUTOINST*/);
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register
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#(
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// Parameters
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.C_WIDTH (64 + 1),
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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hdr_register_63_0
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(
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// Outputs
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.RD_DATA ({_wRxcHdr[C_STRADDLE_W-1:0], _wRxcHdrValid}),
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// Inputs
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.WR_DATA ({__wRxcHdr[C_STRADDLE_W-1:0], __wRxcHdrValid}),
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.WR_EN (__wRxcHdrSOP | rStraddledSOP),
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.RST_IN (RST_IN), // TODO: Remove
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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register
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#(
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// Parameters
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.C_WIDTH (64),
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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hdr_register_127_64
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(
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// Outputs
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.RD_DATA (_wRxcHdr[`TLP_MAXHDR_W-1:C_STRADDLE_W]),
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// Inputs
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.WR_DATA (__wRxcHdr[`TLP_MAXHDR_W-1:C_STRADDLE_W]),
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.WR_EN (__wRxcHdrSOP | rStraddledSOP | rStraddledSOPSplit), // Non straddled start, Straddled, or straddled split
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.RST_IN (RST_IN), // TODO: Remove
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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register
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#(
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// Parameters
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.C_WIDTH (2),
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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sf4dwh// TODO: Rename
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(
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// Outputs
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.RD_DATA ({_wRxcHdrSOPStraddle,_wRxcHdrSOP}),
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// Inputs
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.WR_DATA ({rStraddledSOP,__wRxcHdrSOP}),
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.WR_EN (1),
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.RST_IN (RST_IN), // TODO: Remove
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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// ----- Computation Register -----
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register
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#(
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// Parameters
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.C_WIDTH (128 + 4),/* TODO: TLP_METADATA_W*/
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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metadata
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(// Output
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.RD_DATA ({wRxcHdr,
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wRxcHdrSF, wRxcHdrDataSoff,
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wRxcHdrEF}),
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// Inputs
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.RST_IN (0),
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.WR_DATA ({_wRxcHdr,
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_wRxcHdrSF, _wRxcHdrDataSoff[1:0],
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_wRxcHdrEF}),
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.WR_EN (1),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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register
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#(
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// Parameters
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.C_WIDTH (3+8),
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.C_VALUE (0)
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/*AUTOINSTPARAM*/)
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metadata_valid
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(// Output
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.RD_DATA ({wRxcHdrValid,
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wRxcHdrSCP, wRxcHdrMCP,
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wRxcHdrEndMask, wRxcHdrStartMask}),
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// Inputs
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.RST_IN (RST_IN),
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.WR_DATA ({_wRxcHdrValid,
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_wRxcHdrSCP, _wRxcHdrMCP,
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_wRxcHdrEndMask, _wRxcHdrStartMask}), // Need to invert the start mask
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.WR_EN (1),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK));
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offset_to_mask
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#(// Parameters
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.C_MASK_SWAP (0),
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.C_MASK_WIDTH (4)
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/*AUTOINSTPARAM*/)
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o2m_ef
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(
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// Outputs
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.MASK (_wRxcHdrEndMask),
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// Inputs
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.OFFSET_ENABLE (_wRxcHdrEF),
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.OFFSET (_wRxcHdrDataEoff)
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/*AUTOINST*/);
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pipeline
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#(
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// Parameters
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.C_DEPTH (C_RX_OUTPUT_STAGES),
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.C_WIDTH (C_OUTPUT_STAGE_WIDTH),
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.C_USE_MEMORY (0)
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/*AUTOINSTPARAM*/)
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output_pipeline
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(
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// Outputs
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.WR_DATA_READY (), // Pinned to 1
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.RD_DATA ({RXC_DATA_WORD_ENABLE, RXC_DATA_START_FLAG, RXC_DATA_START_OFFSET,
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RXC_DATA_END_FLAG, RXC_META_TAG, RXC_META_TYPE,
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RXC_META_ADDR, RXC_META_COMPLETER_ID, RXC_META_BYTES_REMAINING,
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RXC_META_LENGTH, RXC_META_EP}),
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.RD_DATA_VALID (RXC_DATA_VALID),
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// Inputs
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.WR_DATA ({wRxcDataWordEnable, wRxcDataStartFlag, wRxcDataStartOffset,
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wRxcDataEndFlag, wRxcMetaTag, wRxcMetaType,
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wRxcMetaAddr, wRxcMetaCompleterId, wRxcMetaBytesRemaining,
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wRxcMetaLength, wRxcMetaEP}),
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.WR_DATA_VALID (wRxcDataValid),
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.RD_DATA_READY (1'b1),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN));
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endmodule
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// Local Variables:
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// verilog-library-directories:("." "../../../common")
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// End:
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