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118 lines
4.9 KiB
Verilog
118 lines
4.9 KiB
Verilog
// ----------------------------------------------------------------------
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// Copyright (c) 2015, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Filename: tx_engine_selector.v
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// Version: 1.00.a
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// Verilog Standard: Verilog-2001
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// Description: Searches for read and write requests.
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// PCIe Endpoint core.
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// Author: Matt Jacobsen
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// History: @mattj: Version 2.0
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// Additional Comments:
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//-----------------------------------------------------------------------------
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`timescale 1ns/1ns
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module tx_engine_selector
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#(
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parameter C_NUM_CHNL = 4'd12
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)
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(
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input CLK,
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input RST,
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input [C_NUM_CHNL-1:0] REQ_ALL, // Write requests
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output REQ, // Write request
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output [3:0] CHNL// Write channel
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);
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reg [3:0] rReqChnl=0, _rReqChnl=0;
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reg [3:0] rReqChnlNext=0, _rReqChnlNext=0;
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reg rReqChnlsSame=0, _rReqChnlsSame=0;
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reg [3:0] rChnlNext=0, _rChnlNext=0;
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reg [3:0] rChnlNextNext=0, _rChnlNextNext=0;
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reg rChnlNextDfrnt=0, _rChnlNextDfrnt=0;
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reg rChnlNextNextOn=0, _rChnlNextNextOn=0;
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wire wChnlNextNextOn;
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reg rReq=0, _rReq=0;
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wire wReq;// = (REQ_ALL>>(rReqChnl));
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reg rReqChnlNextUpdated=0, _rReqChnlNextUpdated=0;
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assign wReq = REQ_ALL[rReqChnl];
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assign wChnlNextNextOn = REQ_ALL[rChnlNextNext];
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assign REQ = rReq;
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assign CHNL = rReqChnl;
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// Search for the next request so that we can move onto it immediately after
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// the current channel has released its request.
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always @ (posedge CLK) begin
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rReq <= #1 (RST ? 1'd0 : _rReq);
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rReqChnl <= #1 (RST ? 4'd0 : _rReqChnl);
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rReqChnlNext <= #1 (RST ? 4'd0 : _rReqChnlNext);
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rChnlNext <= #1 (RST ? 4'd0 : _rChnlNext);
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rChnlNextNext <= #1 (RST ? 4'd0 : _rChnlNextNext);
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rChnlNextDfrnt <= #1 (RST ? 1'd0 : _rChnlNextDfrnt);
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rChnlNextNextOn <= #1 (RST ? 1'd0 : _rChnlNextNextOn);
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rReqChnlsSame <= #1 (RST ? 1'd0 : _rReqChnlsSame);
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rReqChnlNextUpdated <= #1 (RST ? 1'd1 : _rReqChnlNextUpdated);
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end
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always @ (*) begin
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// Go through each channel (RR), looking for requests
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_rChnlNextNextOn = wChnlNextNextOn;
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_rChnlNext = rChnlNextNext;
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_rChnlNextNext = (rChnlNextNext == C_NUM_CHNL - 1 ? 4'd0 : rChnlNextNext + 1'd1);
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_rChnlNextDfrnt = (rChnlNextNext != rReqChnl);
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_rReqChnlsSame = (rReqChnlNext == rReqChnl);
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// Save ready channel if it is not the same channel we're currently on
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if (rChnlNextNextOn & rChnlNextDfrnt & rReqChnlsSame & !rReqChnlNextUpdated) begin
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_rReqChnlNextUpdated = 1;
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_rReqChnlNext = rChnlNext;
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end
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else begin
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_rReqChnlNextUpdated = 0;
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_rReqChnlNext = rReqChnlNext;
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end
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// Assign the new channel
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_rReq = wReq;
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_rReqChnl = (!rReq ? rReqChnlNext : rReqChnl);
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end
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endmodule
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