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411 lines
18 KiB
Verilog
411 lines
18 KiB
Verilog
// ----------------------------------------------------------------------
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// Copyright (c) 2015, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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`define FMT_TXENGUPR32_WR32 7'b10_00000
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`define FMT_TXENGUPR32_RD32 7'b00_00000
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`define FMT_TXENGUPR32_WR64 7'b11_00000
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`define FMT_TXENGUPR32_RD64 7'b01_00000
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`define S_TXENGUPR32_MAIN_IDLE 6'b00_0001
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`define S_TXENGUPR32_MAIN_RD 6'b00_0010
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`define S_TXENGUPR32_MAIN_WR 6'b00_0100
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`define S_TXENGUPR32_MAIN_WAIT_0 6'b00_1000
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`define S_TXENGUPR32_MAIN_WAIT_1 6'b01_0000
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`define S_TXENGUPR32_MAIN_WAIT_2 6'b10_0000
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`define S_TXENGUPR32_CAP_RD_WR 4'b0001
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`define S_TXENGUPR32_CAP_WR_RD 4'b0010
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`define S_TXENGUPR32_CAP_CAP 4'b0100
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`define S_TXENGUPR32_CAP_REL 4'b1000
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`include "trellis.vh"
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`timescale 1ns/1ns
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module tx_multiplexer_32
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#(
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parameter C_PCI_DATA_WIDTH = 9'd32,
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parameter C_NUM_CHNL = 4'd12,
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parameter C_TAG_WIDTH = 5, // Number of outstanding requests
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parameter C_VENDOR = "XILINX"
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)
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(
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input CLK,
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input RST_IN,
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input [C_NUM_CHNL-1:0] WR_REQ, // Write request
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input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] WR_ADDR, // Write address
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input [(C_NUM_CHNL*`SIG_LEN_W)-1:0] WR_LEN, // Write data length
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input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] WR_DATA, // Write data
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output [C_NUM_CHNL-1:0] WR_DATA_REN, // Write data read enable
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output [C_NUM_CHNL-1:0] WR_ACK, // Write request has been accepted
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input [C_NUM_CHNL-1:0] RD_REQ, // Read request
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input [(C_NUM_CHNL*2)-1:0] RD_SG_CHNL, // Read request channel for scatter gather lists
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input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] RD_ADDR, // Read request address
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input [(C_NUM_CHNL*`SIG_LEN_W)-1:0] RD_LEN, // Read request length
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output [C_NUM_CHNL-1:0] RD_ACK, // Read request has been accepted
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output [5:0] INT_TAG, // Internal tag to exchange with external
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output INT_TAG_VALID, // High to signal tag exchange
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input [C_TAG_WIDTH-1:0] EXT_TAG, // External tag to provide in exchange for internal tag
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input EXT_TAG_VALID, // High to signal external tag is valid
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output TX_ENG_RD_REQ_SENT, // Read completion request issued
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input RXBUF_SPACE_AVAIL,
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// Interface: TXR Engine
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output TXR_DATA_VALID,
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output [C_PCI_DATA_WIDTH-1:0] TXR_DATA,
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output TXR_DATA_START_FLAG,
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output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
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output TXR_DATA_END_FLAG,
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output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
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input TXR_DATA_READY,
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output TXR_META_VALID,
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output [`SIG_FBE_W-1:0] TXR_META_FDWBE,
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output [`SIG_LBE_W-1:0] TXR_META_LDWBE,
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output [`SIG_ADDR_W-1:0] TXR_META_ADDR,
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output [`SIG_LEN_W-1:0] TXR_META_LENGTH,
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output [`SIG_TAG_W-1:0] TXR_META_TAG,
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output [`SIG_TC_W-1:0] TXR_META_TC,
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output [`SIG_ATTR_W-1:0] TXR_META_ATTR,
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output [`SIG_TYPE_W-1:0] TXR_META_TYPE,
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output TXR_META_EP,
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input TXR_META_READY
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);
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// Local parameters
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localparam C_DATA_DELAY = 6'd1; // Delays read/write params to accommodate tx_port_buffer delay and tx_engine_formatter delay.
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(* syn_encoding = "user" *)
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(* fsm_encoding = "user" *)
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reg [5:0] rMainState=`S_TXENGUPR32_MAIN_IDLE, _rMainState=`S_TXENGUPR32_MAIN_IDLE;
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reg [3:0] rCountChnl=0, _rCountChnl=0;
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reg [C_TAG_WIDTH-1:0] rCountTag=0, _rCountTag=0;
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reg [9:0] rCount=0, _rCount=0;
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reg rCountDone=0, _rCountDone=0;
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reg rCountStart=0, _rCountStart=0;
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reg rCount32=0, _rCount32=0;
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reg [C_NUM_CHNL-1:0] rWrDataRen=0, _rWrDataRen=0;
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reg rTxEngRdReqAck, _rTxEngRdReqAck;
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wire wRdReq;
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wire [3:0] wRdReqChnl;
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wire wWrReq;
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wire [3:0] wWrReqChnl;
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wire wRdAck;
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wire [3:0] wCountChnl;
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wire [11:0] wCountChnlShiftDW = (wCountChnl*C_PCI_DATA_WIDTH); // Mult can exceed 9 bits, so make this a wire
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wire [63:0] wRdAddr;
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wire [9:0] wRdLen;
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wire [1:0] wRdSgChnl;
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wire [63:0] wWrAddr;
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wire [9:0] wWrLen;
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wire [C_PCI_DATA_WIDTH-1:0] wWrData;
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reg [3:0] rRdChnl=0, _rRdChnl=0;
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reg [61:0] rRdAddr=62'd0, _rRdAddr=62'd0;
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reg [9:0] rRdLen=0, _rRdLen=0;
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reg [1:0] rRdSgChnl=0, _rRdSgChnl=0;
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reg [3:0] rWrChnl=0, _rWrChnl=0;
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reg [61:0] rWrAddr=62'd0, _rWrAddr=62'd0;
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reg [9:0] rWrLen=0, _rWrLen=0;
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reg [C_PCI_DATA_WIDTH-1:0] rWrData={C_PCI_DATA_WIDTH{1'd0}}, _rWrData={C_PCI_DATA_WIDTH{1'd0}};
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(* syn_encoding = "user" *)
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(* fsm_encoding = "user" *)
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reg [3:0] rCapState=`S_TXENGUPR32_CAP_RD_WR, _rCapState=`S_TXENGUPR32_CAP_RD_WR;
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reg [C_NUM_CHNL-1:0] rRdAck=0, _rRdAck=0;
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reg [C_NUM_CHNL-1:0] rWrAck=0, _rWrAck=0;
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reg rIsWr=0, _rIsWr=0;
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reg [5:0] rCapChnl=0, _rCapChnl=0;
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reg [61:0] rCapAddr=62'd0, _rCapAddr=62'd0;
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reg rCapAddr64=0, _rCapAddr64=0;
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reg [9:0] rCapLen=0, _rCapLen=0;
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reg rCapIsWr=0, _rCapIsWr=0;
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reg rExtTagReq=0, _rExtTagReq=0;
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reg [C_TAG_WIDTH-1:0] rExtTag=0, _rExtTag=0;
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reg [C_DATA_DELAY-1:0] rWnR=0, _rWnR=0;
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reg [(C_DATA_DELAY*4)-1:0] rChnl=0, _rChnl=0;
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reg [(C_DATA_DELAY*8)-1:0] rTag=0, _rTag=0;
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reg [(C_DATA_DELAY*62)-1:0] rAddr=0, _rAddr=0;
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reg [C_DATA_DELAY-1:0] rAddr64=0, _rAddr64=0;
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reg [(C_DATA_DELAY*10)-1:0] rLen=0, _rLen=0;
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reg [C_DATA_DELAY-1:0] rLenEQ1=0, _rLenEQ1=0;
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reg [C_DATA_DELAY-1:0] rValid=0, _rValid=0;
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reg [C_DATA_DELAY-1:0] rDone=0, _rDone=0;
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reg [C_DATA_DELAY-1:0] rStart=0, _rStart=0;
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assign wRdAddr = RD_ADDR[wRdReqChnl * `SIG_ADDR_W +: `SIG_ADDR_W];
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assign wRdLen = RD_LEN[wRdReqChnl * `SIG_LEN_W +: `SIG_LEN_W];
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assign wRdSgChnl = RD_SG_CHNL[wRdReqChnl * 2 +: 2];
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assign wWrAddr = WR_ADDR[wWrReqChnl * `SIG_ADDR_W +: `SIG_ADDR_W];
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assign wWrLen = WR_LEN[wWrReqChnl * `SIG_LEN_W +: `SIG_LEN_W];
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assign wWrData = WR_DATA[wCountChnl * C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];
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assign WR_DATA_REN = rWrDataRen;
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assign WR_ACK = rWrAck;
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assign RD_ACK = rRdAck;
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assign INT_TAG = {rRdSgChnl, rRdChnl};
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assign INT_TAG_VALID = rExtTagReq;
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assign TX_ENG_RD_REQ_SENT = rTxEngRdReqAck;
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assign wRdAck = (wRdReq & EXT_TAG_VALID & RXBUF_SPACE_AVAIL);
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// Search for the next request so that we can move onto it immediately after
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// the current channel has released its request.
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tx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selRd (.RST(RST_IN), .CLK(CLK), .REQ_ALL(RD_REQ), .REQ(wRdReq), .CHNL(wRdReqChnl));
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tx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selWr (.RST(RST_IN), .CLK(CLK), .REQ_ALL(WR_REQ), .REQ(wWrReq), .CHNL(wWrReqChnl));
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// Buffer shift-selected channel request signals and FIFO data.
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always @ (posedge CLK) begin
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rRdChnl <= #1 _rRdChnl;
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rRdAddr <= #1 _rRdAddr;
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rRdLen <= #1 _rRdLen;
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rRdSgChnl <= #1 _rRdSgChnl;
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rWrChnl <= #1 _rWrChnl;
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rWrAddr <= #1 _rWrAddr;
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rWrLen <= #1 _rWrLen;
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rWrData <= #1 _rWrData;
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end
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always @ (*) begin
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_rRdChnl = wRdReqChnl;
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_rRdAddr = wRdAddr[63:2];
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_rRdLen = wRdLen;
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_rRdSgChnl = wRdSgChnl;
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_rWrChnl = wWrReqChnl;
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_rWrAddr = wWrAddr[63:2];
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_rWrLen = wWrLen;
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_rWrData = wWrData;
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end
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// Accept requests when the selector indicates. Capture the buffered
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// request parameters for hand-off to the formatting pipeline. Then
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// acknowledge the receipt to the channel so it can deassert the
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// request, and let the selector choose another channel.
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always @ (posedge CLK) begin
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rCapState <= #1 (RST_IN ? `S_TXENGUPR32_CAP_RD_WR : _rCapState);
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rRdAck <= #1 (RST_IN ? {C_NUM_CHNL{1'd0}} : _rRdAck);
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rWrAck <= #1 (RST_IN ? {C_NUM_CHNL{1'd0}} : _rWrAck);
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rIsWr <= #1 _rIsWr;
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rCapChnl <= #1 _rCapChnl;
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rCapAddr <= #1 _rCapAddr;
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rCapAddr64 <= #1 _rCapAddr64;
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rCapLen <= #1 _rCapLen;
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rCapIsWr <= #1 _rCapIsWr;
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rExtTagReq <= #1 _rExtTagReq;
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rExtTag <= #1 _rExtTag;
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rTxEngRdReqAck <= #1 _rTxEngRdReqAck;
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end
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always @ (*) begin
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_rCapState = rCapState;
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_rRdAck = rRdAck;
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_rWrAck = rWrAck;
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_rIsWr = rIsWr;
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_rCapChnl = rCapChnl;
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_rCapAddr = rCapAddr;
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_rCapAddr64 = (rCapAddr[61:30] != 0);
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_rCapLen = rCapLen;
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_rCapIsWr = rCapIsWr;
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_rExtTagReq = rExtTagReq;
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_rExtTag = rExtTag;
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_rTxEngRdReqAck = rTxEngRdReqAck;
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case (rCapState)
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`S_TXENGUPR32_CAP_RD_WR : begin
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_rIsWr = !wRdReq;
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_rRdAck = ((wRdAck)<<wRdReqChnl);
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_rTxEngRdReqAck = wRdAck;
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_rExtTagReq = wRdAck;
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_rCapState = (wRdAck ? `S_TXENGUPR32_CAP_CAP : `S_TXENGUPR32_CAP_WR_RD);
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end
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`S_TXENGUPR32_CAP_WR_RD : begin
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_rIsWr = wWrReq;
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_rWrAck = (wWrReq<<wWrReqChnl);
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_rCapState = (wWrReq ? `S_TXENGUPR32_CAP_CAP : `S_TXENGUPR32_CAP_RD_WR);
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end
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`S_TXENGUPR32_CAP_CAP : begin
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_rTxEngRdReqAck = 0;
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_rRdAck = 0;
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_rWrAck = 0;
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_rCapIsWr = rIsWr;
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_rExtTagReq = 0;
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_rExtTag = EXT_TAG;
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if (rIsWr) begin
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_rCapChnl = {2'd0, rWrChnl};
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_rCapAddr = rWrAddr;
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_rCapLen = rWrLen;
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end
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else begin
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_rCapChnl = {rRdSgChnl, rRdChnl};
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_rCapAddr = rRdAddr;
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_rCapLen = rRdLen;
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end
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_rCapState = `S_TXENGUPR32_CAP_REL;
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end
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`S_TXENGUPR32_CAP_REL : begin
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// Push into the formatting pipeline when ready
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if (TXR_META_READY & rMainState[0]) // S_TXENGUPR32_MAIN_IDLE
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_rCapState = (`S_TXENGUPR32_CAP_WR_RD>>(rCapIsWr)); // Changes to S_TXENGUPR32_CAP_RD_WR
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end
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default : begin
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_rCapState = `S_TXENGUPR32_CAP_RD_WR;
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end
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endcase
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end
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// Start the read/write when space is available in the output FIFO and when
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// request parameters have been captured (i.e. a pending request).
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always @ (posedge CLK) begin
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rMainState <= #1 (RST_IN ? `S_TXENGUPR32_MAIN_IDLE : _rMainState);
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rCount <= #1 _rCount;
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rCountDone <= #1 _rCountDone;
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rCountStart <= #1 _rCountStart;
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rCountChnl <= #1 _rCountChnl;
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rCountTag <= #1 _rCountTag;
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rCount32 <= #1 _rCount32;
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rWrDataRen <= #1 _rWrDataRen;
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end
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always @ (*) begin
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_rMainState = rMainState;
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_rCount = rCount;
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_rCountDone = rCountDone;
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_rCountChnl = rCountChnl;
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_rCountTag = rCountTag;
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_rCount32 = rCount32;
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_rWrDataRen = rWrDataRen;
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_rCountStart = 0;
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case (rMainState)
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`S_TXENGUPR32_MAIN_IDLE : begin
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_rCount = rCapLen;
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_rCountDone = (rCapLen == 10'd1);
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_rCountChnl = rCapChnl[3:0];
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_rCountTag = rExtTag;
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_rCount32 = (rCapAddr[61:30] == 0);
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_rWrDataRen = ((TXR_META_READY & rCapState[3] & rCapIsWr)<<(rCapChnl[3:0])); // S_TXENGUPR32_CAP_REL
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_rCountStart = (TXR_META_READY & rCapState[3]);
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if (TXR_META_READY & rCapState[3]) // S_TXENGUPR32_CAP_REL
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_rMainState = (`S_TXENGUPR32_MAIN_RD<<(rCapIsWr)); // Change to S_TXENGUPR32_MAIN_WR;
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end
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`S_TXENGUPR32_MAIN_RD : begin
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_rMainState = (`S_TXENGUPR32_MAIN_WAIT_1<<(rCount32)); // Change to S_TXENGUPR32_MAIN_WAIT_2
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end
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`S_TXENGUPR32_MAIN_WR : begin
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_rCount = rCount - 1'd1;
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_rCountDone = (rCount == 2'd2);
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if (rCountDone) begin
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_rWrDataRen = 0;
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_rMainState = (`S_TXENGUPR32_MAIN_WAIT_0<<(rCount32)); // Change to S_TXENGUPR32_MAIN_WAIT_1
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end
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end
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`S_TXENGUPR32_MAIN_WAIT_0 : begin
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_rMainState = `S_TXENGUPR32_MAIN_WAIT_1;
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end
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`S_TXENGUPR32_MAIN_WAIT_1 : begin
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_rMainState = `S_TXENGUPR32_MAIN_WAIT_2;
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end
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`S_TXENGUPR32_MAIN_WAIT_2 : begin
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_rMainState = `S_TXENGUPR32_MAIN_IDLE;
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end
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default : begin
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_rMainState = `S_TXENGUPR32_MAIN_IDLE;
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end
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endcase
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end
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// Shift in the captured parameters and valid signal every cycle.
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// This pipeline will keep the formatter busy.
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assign wCountChnl = rCountChnl[3:0];
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always @ (posedge CLK) begin
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rWnR <= #1 _rWnR;
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rChnl <= #1 _rChnl;
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rTag <= #1 _rTag;
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rAddr <= #1 _rAddr;
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rAddr64 <= #1 _rAddr64;
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rLen <= #1 _rLen;
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rLenEQ1 <= #1 _rLenEQ1;
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rValid <= #1 _rValid;
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end
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always @ (*) begin
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_rWnR = ((rWnR<<1) | rCapIsWr);
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_rChnl = ((rChnl<<4) | rCountChnl);
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_rTag = ((rTag<<8) | (8'd0 | rCountTag));
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_rAddr = ((rAddr<<62) | rCapAddr);
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_rAddr64 = ((rAddr64<<1) | rCapAddr64);
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_rLen = ((rLen<<10) | rCapLen);
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_rLenEQ1 = ((rLenEQ1<<1) | (rCapLen == 10'd1));
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_rValid = ((rValid<<1) | (rMainState[2] | rMainState[1])); // S_TXENGUPR64_MAIN_RD | S_TXENGUPR64_MAIN_WR
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_rDone = rDone<<1 | rCountDone;
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_rStart = rStart<<1 | rCountStart;
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end
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assign TXR_DATA = rWrData;
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assign TXR_DATA_VALID = rValid[(C_DATA_DELAY-1)*1 +:1];
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assign TXR_DATA_START_FLAG = rStart[(C_DATA_DELAY-1)*1 +:1];
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assign TXR_DATA_START_OFFSET = 0;
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assign TXR_DATA_END_FLAG = rDone[(C_DATA_DELAY-1)*1 +:1];
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assign TXR_DATA_END_OFFSET = rLen[(C_DATA_DELAY-1)*10 +:`SIG_OFFSET_W] - 1;
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assign TXR_META_VALID = rCountStart;
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assign TXR_META_TYPE = rCapIsWr ? `TRLS_REQ_WR : `TRLS_REQ_RD;
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assign TXR_META_ADDR = {rCapAddr,2'b00};
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assign TXR_META_LENGTH = rCapLen;
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assign TXR_META_LDWBE = rCapLen == 10'd1 ? 0 : 4'b1111;
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assign TXR_META_FDWBE = 4'b1111;
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assign TXR_META_TAG = rCountTag;
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assign TXR_META_EP = 1'b0;
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assign TXR_META_ATTR = 3'b110;
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assign TXR_META_TC = 0;
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endmodule
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