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riffa/fpga/riffa_hdl
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Dustin Richmond e2f3abe01b Fixed a bug in RIFFA 2.2 for the Classic Xilinx 128-bit interface. 
Bug caused received 128-bit Request Headers without payload to signal data word valid one cycle early. May not be a final fix. Unlikely to affect current users.
2015-07-21 15:46:36 -07:00
..
altera.vh
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
async_fifo_fwft.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
async_fifo.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
channel_32.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
channel_64.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
channel_128.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
channel.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
chnl_tester.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
counter.v
Fixed a small bit-width related issue in counter.v.
2015-07-15 16:44:50 -07:00
cross_domain_signal.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
demux.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
engine_layer.v
Finished wiring reset logic in the Engine Layer (untested)
2015-07-16 16:26:05 -07:00
ff.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
fifo_packer_32.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
fifo_packer_64.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
fifo_packer_128.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
fifo.v
Added a parameter C_VALUE to shiftreg.v and changed all declarations.
2015-07-15 17:26:00 -07:00
functions.vh
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
interrupt_controller.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
interrupt.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
mux.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
offset_flag_to_one_hot.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
offset_to_mask.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
one_hot_mux.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
pipeline.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
ram_1clk_1w_1r.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
ram_2clk_1w_1r.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
recv_credit_flow_ctrl.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
register.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
registers.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
reorder_queue_input.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
reorder_queue_output.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
reorder_queue.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
resetter.v
Adding resetter.v, a new module that controls the reset logic in riffa.v.
2015-07-15 17:27:17 -07:00
riffa.v
Adding resetter.v, a new module that controls the reset logic in riffa.v.
2015-07-15 17:27:17 -07:00
riffa.vh
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
rotate.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
rx_engine_classic.v
Finished wiring reset logic in the Engine Layer (untested)
2015-07-16 16:26:05 -07:00
rx_engine_ultrascale.v
Finished wiring reset logic in the Engine Layer (untested)
2015-07-16 16:26:05 -07:00
rx_port_32.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
rx_port_64.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
rx_port_128.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
rx_port_channel_gate.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
rx_port_reader.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
rx_port_requester_mux.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
rxc_engine_128.v
Finished wiring reset logic in the Engine Layer (untested)
2015-07-16 16:26:05 -07:00
rxc_engine_classic.v
Finished wiring reset logic in the Engine Layer (untested)
2015-07-16 16:26:05 -07:00
rxc_engine_ultrascale.v
Finished wiring reset logic in the Engine Layer (untested)
2015-07-16 16:26:05 -07:00
rxr_engine_128.v
Fixed a bug in RIFFA 2.2 for the Classic Xilinx 128-bit interface.
2015-07-21 15:46:36 -07:00
rxr_engine_classic.v
Finished wiring reset logic in the Engine Layer (untested)
2015-07-16 16:26:05 -07:00
rxr_engine_ultrascale.v
Finished wiring reset logic in the Engine Layer (untested)
2015-07-16 16:26:05 -07:00
schedules.vh
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
scsdpram.v
Added a parameter C_VALUE to shiftreg.v and changed all declarations.
2015-07-15 17:26:00 -07:00
sg_list_reader_32.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
sg_list_reader_64.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
sg_list_reader_128.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
sg_list_requester.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
shiftreg.v
Added a parameter C_VALUE to shiftreg.v and changed all declarations.
2015-07-15 17:26:00 -07:00
sync_fifo.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
syncff.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tlp.vh
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
translation_altera.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
translation_xilinx.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
trellis.vh
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_alignment_pipeline.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_data_fifo.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_data_pipeline.v
Finished wiring reset logic in the Engine Layer (untested)
2015-07-16 16:26:05 -07:00
tx_data_shift.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_engine_classic.v
Finished wiring reset logic in the Engine Layer (untested)
2015-07-16 16:26:05 -07:00
tx_engine_selector.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_engine_ultrascale.v
Finished wiring reset logic in the Engine Layer (untested)
2015-07-16 16:26:05 -07:00
tx_engine.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_hdr_fifo.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_multiplexer_32.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_multiplexer_64.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_multiplexer_128.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_multiplexer.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_port_32.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_port_64.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_port_128.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_port_buffer_32.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_port_buffer_64.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_port_buffer_128.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_port_channel_gate_32.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_port_channel_gate_64.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_port_channel_gate_128.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_port_monitor_32.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_port_monitor_64.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_port_monitor_128.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
tx_port_writer.v
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
txc_engine_classic.v
Finished wiring reset logic in the Engine Layer (untested)
2015-07-16 16:26:05 -07:00
txc_engine_ultrascale.v
Added a S_AXIS_**_TREADY Check on the reset logic in the ultrascale engines.
2015-07-17 16:54:06 -07:00
txr_engine_classic.v
Finished wiring reset logic in the Engine Layer (untested)
2015-07-16 16:26:05 -07:00
txr_engine_ultrascale.v
Added a S_AXIS_**_TREADY Check on the reset logic in the ultrascale engines.
2015-07-17 16:54:06 -07:00
types.vh
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
ultrascale.vh
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
widths.vh
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00
xilinx.vh
Initial commit of RIFFA development repository (RIFFA 2.2)
2015-05-04 14:50:57 -07:00