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This logic will allow us to reset the TX pipeline safely, and still transmit the status completion. This is a feature requested by the NetFPGA team.
92 lines
3.9 KiB
Verilog
92 lines
3.9 KiB
Verilog
// ----------------------------------------------------------------------
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// Copyright (c) 2015, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Filename: resetter.v
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// Version: 1.00.a
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// Verilog Standard: Verilog-2001
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// Description: A simple reset controller.
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// Author: Dustin Richmond (@darichmond)
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//-----------------------------------------------------------------------------
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`timescale 1ns/1ns
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`include "functions.vh"
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module resetter
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#(parameter C_RST_COUNT = 10,
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parameter C_RST_USE_SHREG = 0)
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(input CLK,
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input RST_IN,
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output RST_OUT);
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localparam C_CLOG2_RST_COUNT = clog2s(C_RST_COUNT);
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localparam C_CEIL2_RST_COUNT = 1 << C_CLOG2_RST_COUNT;
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generate
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wire [C_RST_COUNT-1:0] wRstShift;
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if(C_RST_USE_SHREG > 0) begin : rst_shreg
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shiftreg
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#(// Parameters
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.C_DEPTH (C_RST_COUNT),
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.C_WIDTH (1),
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.C_VALUE (1'b1))
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rst_shreg
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(// Outputs
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.RD_DATA (wRstShift),
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// Inputs
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.WR_DATA (0),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN));
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assign RST_OUT = wRstShift[C_RST_COUNT-1];
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end else begin : rst_counter // block: rst_shreg
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wire [C_CLOG2_RST_COUNT-1:0] wRstCount;
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counter
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#(// Parameters
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.C_MAX_VALUE (C_CEIL2_RST_COUNT - 1),
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.C_SAT_VALUE (C_CEIL2_RST_COUNT - 1),
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.C_RST_VALUE (C_CEIL2_RST_COUNT - C_RST_COUNT)
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/*AUTOINSTPARAM*/)
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rst_counter
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(// Outputs
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.VALUE (wRstCount),
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// Inputs
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.ENABLE (1'b1),
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/*AUTOINST*/
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// Inputs
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.CLK (CLK),
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.RST_IN (RST_IN));
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assign RST_OUT = wRstCount[C_CLOG2_RST_COUNT-1];
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end
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endgenerate
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endmodule
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