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66 lines
2.8 KiB
Systemverilog
66 lines
2.8 KiB
Systemverilog
// ----------------------------------------------------------------------
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// Copyright (c) 2015, The Regents of the University of California All
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// rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// * Neither the name of The Regents of the University of California
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// nor the names of its contributors may be used to endorse or
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// promote products derived from this software without specific
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// prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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// DAMAGE.
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// ----------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Filename: xilinx.vh
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// Version: 1.0
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// Verilog Standard: Verilog-2001
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// Description: The xilinx.vh file is a header file that defines
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// various Xilinx-specific primitives.
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// Author: Dustin Richmond (@darichmond)
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//-----------------------------------------------------------------------------
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`ifndef __XILINX_VH
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`define __XILINX_VH 1
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`define SIG_XIL_TX_TUSER_W 4
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`define SIG_XIL_RX_TUSER_W 22
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`define SIG_FC_SEL_W 3 // Xilinx specific
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`define SIG_FC_SEL_RX_BUF_AVAIL_V 3'b000
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`define SIG_FC_SEL_RX_MAXALLOC_V 3'b001
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`define SIG_FC_SEL_RX_CONSUMED_V 3'b010
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`define SIG_FC_SEL_TX_CRED_AVAIL_V 3'b100
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`define SIG_FC_SEL_TX_MAXALLOC_V 3'b101
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`define SIG_FC_SEL_TX_CONSUMED_V 3'b110
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`define CFG_COMMAND_BUSMSTR_R 2
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`define CFG_LSTATUS_LWIDTH_R 9:4
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`define CFG_LSTATUS_LRATE_R 3:0
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`define CFG_DCOMMAND_MAXREQ_R 14:12
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`define CFG_DCOMMAND_MAXPAY_R 7:5
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`define CFG_LCOMMAND_RCB_R 3
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`endif
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