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study/pwm/rtl/ctrl.v.bak

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2020-06-09 15:48:03 +08:00
module ctrl(
clk,
rst_n,
pwm_out
);
input clk;
input rst_n;
wire en_pwm;
wire [15:0] pwm_arr;
wire [15:0] pwm_ccr;
output pwm_out;
pwm(
.clk(),
.rst_n(),
.en_pwm(),
.pwm_arr(),
.pwm_ccr(),
.pwm_out()
);
endmodule